Digital signal decoding circuit and decoding method

Claim 2

A digital signal decoding circuit comprising: detection means for detecting data indicative of a DC level of a received digital signal in each bit of interest of the received digital signal; means for determining a change form of the received digital signal, and determining when said change form indicates a maximum signal to produce a first indication, and a maximum signal to produce a second indication; reference signal generation means for generating a reference signal having a signal value according to the data associated with the DC level detected by said detection means at a time of said first or second indications; and discrimination means for comparing a signal value of the received digital signal with the signal value of the reference signal generated by said reference signal generation means to discriminate a code of the each bit of interest.

Claim 3

A circuit according to claim 1, wherein said detection means comprises: means for obtaining a maximum value and a minimum value of an amplitude of each bit of interest of the received digital signal at times of said first and second indications by said change rate determining means; and means for obtaining a central value of the amplitude of the received digital signal on the basis of the maximum and minimum values detected by said maximum and minimum value detecting means.

Claim 4

A circuit according to claim 1, wherein said detection means comprises: means for detecting either maximum or minimum values of an amplitude of each bit of interest of the received digital signal at times of said first and second indications by said change rate determining means; and means for adding a predetermined offset value to the minimum value in response to a detection of the minimum value or subtracting the predetermined offset value from the maximum value in response to a detection of the maximum value to obtain a central value of the amplitude of the received digital signal.

Claim 5

A digital signal decoding method comprising the steps of: detecting data associated with a DC level of a received digital signal in each bit of interest of the received digital signal; means for determining a change form of the received digital signal, and determining when said change form indicates a maximum signal to produce a first indication, and a minimum signal to produce a second indication; generating a reference signal having a signal value according to the data associated with the DC level detected by the detecting step at a time of said first or second indications; and comparing a signal value of the received digital signal with the signal value of the reference signal to discriminate a code of the bit of interest.

Claim 6

A digital signal decoding method comprising the steps of: detecting data associated with a DC level of a received digital signal in each bit of interest of the received digital signal; means for determining a change form of the received digital signal, and determining when said change form indicates a maximum signal to produce a first indication, and a minimum signal to produce a second indication; generating a reference signal having a signal value according to the data associated with the DC level detected by the detecting step at a time of said first or second indications; and comparing a signal value of the received digital signal with the signal value of the reference signal to discriminate a code of the bit of interest.

Claim 7

A digital signal decoding circuit as in claim 1, further comprising: average value obtaining means for obtaining an average value of the data associated with the DC levels detected at a plurality of bits of interest by said detection means; and wherein said reference signal generating means generates said reference signal having a signal value according to the average value obtained by said average value obtaining means.

Claim 8

A digital signal decoding circuit comprising: detection means for detecting a signal value of an amplitude of each bit of interest of the received digital signal; intermediate value obtaining means for calculating a predetermined offset value with the signal value detected by said detection means to obtain an intermediate value of an amplitude of the received digital signal; average value obtaining means for obtaining an average value of the data associated with the intermediate values obtained at a plurality of bits of interest by said intermediate value obtaining means; reference signal generating means for generating a reference signal having a signal value according to the data associated with the average value obtained by said average value obtaining means; and discrimination means for comparing a signal value of the received digital signal with the signal value of the reference signal generated by said reference signal generation means to discriminate a code of the each bit of interest.

Claim 9

A digital signal decoding circuit comprising: detection means for detecting a signal value of an amplitude of each bit of interest of the received digital signal; intermediate value obtaining means for calculating a predetermined offset value with the signal value detected by said detection means to obtain an intermediate value of an amplitude of the received digital signal; average value obtaining means for obtaining an average value of the data associated with the intermediate values obtained at a plurality of bits of interest by said intermediate value obtaining means; reference signal generating means for generating a reference signal having a signal value according to the data associated with the average value obtained by said average value obtaining means; and discrimination means for comparing a signal value of the received digital signal with the signal value of the reference signal generated by said reference signal generation means to discriminate a code of the each bit of interest.

Claim 10

A digital signal decoding circuit comprising: signal value detection means for detecting a signal value of a received digital signal on the basis of a signal value of a reference signal in each bit of interest of the received digital signal; code discrimination means, every time said signal value detection means detects a signal value at a new bit of interest, for discriminating a code of the new bit of interest of the received digital signal on the basis of the signal value detected at the new bit of interest and a signal value detected at a previous bit of interest; DC data detection means, every time said signal value detection means detects the signal value at the new bit of interest, for generating a parameter value according to the signal value detected at the new bit of interest, and detecting data associated with a DC level of the received digital signal on the basis of the parameter value and the signal value of the new bit of of interest of the received digital signal; average value obtaining means for obtaining an average value of data associated with the DC level detected by said DC data detection means and data associated with a DC level detected at a previous bit of interest; and new reference signal generation means for generating a ne reference signal having a signal value according to the average value obtained by said average value detection means and supplying the new reference signal to said signal value detection means.

Claim 11

A digital signal decoding circuit comprising: signal value detection means for detecting a signal value of a received digital signal on the basis of a signal value of a reference signal in each bit of interest of the received digital signal; code discrimination means, every time said signal value detection means detects a signal value at a new bit of interest, for discriminating a code of the new bit of interest of the received digital signal on the basis of the signal value detected at the new bit of interest and a signal value detected at a previous bit of interest; DC data detection means, every time said signal value detection means detects the signal value at the new bit of interest, for generating a parameter value according to the signal value detected at the new bit of interest, and detecting data associated with a DC level of the received digital signal on the basis of the parameter value and the signal value of the new bit of of interest of the received digital signal; average value obtaining means for obtaining an average value of data associated with the DC level detected by said DC data detection means and data associated with a DC level detected at a previous bit of interest; and new reference signal generation means for generating a ne reference signal having a signal value according to the average value obtained by said average value detection means and supplying the new reference signal to said signal value detection means.

Claim 12

A circuit according to claim 7, wherein said signal value detection means comprises: threshold value generation means for generating a plurality of threshold values on the basis of a signal value of the reference signal; and signal level comparison means for comparing the signal value of the received digital signal with the plurality of threshold values generated by said threshold value generation means in each bit of interest of the received digital signal and outputting comparison results, and said code discrimination means comprises means for discriminating a code of the bit of interest on the basis of the comparison results of the new bit of interest output from said signal level comparison means and the comparison results at least at one previous bit of interest.

Claim 13

A circuit according to claim 7, wherein said DC data detection means comprises: offset value generation means for generating an optimal offset value according to the signal value detected by said signal value detection means; and central value obtaining means for obtaining an amplitude central value of the received digital signal by using the offset value generated by said offset value generation means, and said average value obtaining means comprises: storage means for storing the amplitude central value obtained by said central value obtaining means together with an amplitude central value obtained at least at one previous bit of interest; and arithmetic means for obtaining an average value of a plurality of amplitude central stored in said storage means.

Claim 14

A circuit according to claim 7, wherein said DC data detection means comprises: initial signal value generation means for generating an initial signal value closest to the signal value detected by said signal value detection means; and change amount detection means for detecting a change amount of the signal value of the received digital signal with respect to the initial signal value generated by said initial signal value generation means; said average value obtaining means comprises: storage means for storing the change amount detected by said change amount detection means together with a change amount detected at least at one previous bit of interest; arithmetic means for calculating an average value of a plurality of change amounts stored in said storage means; and said reference signal level generation means comprises means for selectively adding and subtracting the average value of the change amounts calculated by said arithmetic means and from the initial value of the reference signal to generate a reference signal having a signal value according to the calculation output, and supplying the reference signal to said signal value detection means.

Claim 15

A digital signal detecting circuit comprising: detection means for detecting either maximum or minimum values of an amplitude of each bit of interest of the received digital signal; central value obtaining means for adding a predetermined offset value to the minimum value in response to a detection of the minimum value, or subtracting the predetermined offset value from the maximum value in response to a detection of the maximum value to obtain a central value of the amplitude of the received digital signal; reference signal generation means for generating a reference signal having a signal value based on the data associated with the central value obtained by said central value obtaining means; and discrimination means for comparing a signal value of the received digital signal with the signal value of the reference signal generated by said reference signal generation means to discriminate a code of the each bit of interest.

Claim 16

A digital signal detecting circuit comprising: detection means for detecting either maximum or minimum values of an amplitude of each bit of interest of the received digital signal; central value obtaining means for adding a predetermined offset value to the minimum value in response to a detection of the minimum value, or subtracting the predetermined offset value from the maximum value in response to a detection of the maximum value to obtain a central value of the amplitude of the received digital signal; reference signal generation means for generating a reference signal having a signal value based on the data associated with the central value obtained by said central value obtaining means; and discrimination means for comparing a signal value of the received digital signal with the signal value of the reference signal generated by said reference signal generation means to discriminate a code of the each bit of interest.

Claim 17

A digital signal decoding circuit comprising: detection means for detecting data associated with a DC level of a received digital signal in each bit of interest of the received digital signal; storage means for every time the data associated with a DC level at a new bit of interest is detected by said detection means, storing the data associated with the DC level at the new bit of interest together with data associated with a DC level detected at least at one previous bit of interest; average value obtaining means for reading out a plurality of data associated with the DC levels from said storage means and obtaining the average value of the plurality of data; reference signal generating means for generating a reference signal having a signal value according to the average value obtained by said average value obtaining means; and discrimination means for comparing a signal value of the received digital signal with the signal value of the reference signal generated by said reference signal generation means to discriminate a code of a new bit of interest.

Claim 18

A digital signal decoding circuit comprising: detection means for detecting data associated with a DC level of a received digital signal in each bit of interest of the received digital signal; storage means for every time the data associated with a DC level at a new bit of interest is detected by said detection means, storing the data associated with the DC level at the new bit of interest together with data associated with a DC level detected at least at one previous bit of interest; average value obtaining means for reading out a plurality of data associated with the DC levels from said storage means and obtaining the average value of the plurality of data; reference signal generating means for generating a reference signal having a signal value according to the average value obtained by said average value obtaining means; and discrimination means for comparing a signal value of the received digital signal with the signal value of the reference signal generated by said reference signal generation means to discriminate a code of a new bit of interest.

Claim 19

A digital signal decoding circuit comprising: detection means for detecting a signal value of an amplitude of each bit of interest of the received digital signal; intermediate value obtaining means for calculating a predetermined offset value with the signal value detected by said detection means to obtain an intermediate value of an amplitude of the received digital signal; reference signal generation means for generating a reference signal having a signal value according to the data associated with the intermediate value obtained by said intermediate value obtaining means; and discrimination means for comparing a signal value of the received digital signal with the signal value of the reference signal generated by said reference signal generation means to discriminate a code of the each bit of interest.

Claim 20

A digital signal decoding circuit comprising: detection means for detecting a signal value of an amplitude of each bit of interest of the received digital signal; intermediate value obtaining means for calculating a predetermined offset value with the signal value detected by said detection means to obtain an intermediate value of an amplitude of the received digital signal; reference signal generation means for generating a reference signal having a signal value according to the data associated with the intermediate value obtained by said intermediate value obtaining means; and discrimination means for comparing a signal value of the received digital signal with the signal value of the reference signal generated by said reference signal generation means to discriminate a code of the each bit of interest.