Self biasing direct coupled data limiter

Claim 2

In a frequency shift keying receiver having a plurality of radio frequency elements including a discriminator which is the last stage of said elements, said receiver including power switching means coupled to a power source for periodically supplying power to said elements, a limiter interface circuit coupled to said discriminator, comprising: a signal limiter directly coupled to said discriminator; first detection means having an input coupled to said discriminator for detecting a peak or maximum signal magnitude and producing an output signal corresponding thereto; second detection means having an input coupled to said discriminator for detecting a valley or minimum signal magnitude and producing an output signal corresponding thereto; said first and second detection means being coupled to said power switching means and said first and second detection means each include means, responsive to said power switching means, for initializing the magnitudes of the corresponding output signals; and means coupling the output signals from said first and second detection means to said signal limiter to provide a reference signal thereto.

Claim 3

The interface circuit of claim 1, wherein said limiter has a signal input terminal and a reference input terminal, said signal input terminal is directly coupled to said discriminator and said coupling means comprises voltage dividing means for selectively weighting and averaging the output signals from said first and second detection means to provide a bias reference signal to the reference input terminal of said limiter.

Claim 4

The interface circuit of claim 2 wherein said limiter comprises a differential amplifier.

Claim 5

The interface circuit of claim 2 wherein said voltage dividing means provides equal weighting to the output signals from said first and second detection means.

Claim 6

The interface circuit of claim 1 further including signal processing circuitry coupled to the output of said limiter to identify the reception of selective calls.

Claim 7

The interface circuit of claim 5, wherein said limiter has a signal input terminal and a reference input terminal, said signal input terminal is directly coupled to said discriminator, said coupling means comprises voltage dividing means for selectively weighting and averaging the output signals from said first and second detection means to provide a bias reference signal to the reference input terminal of said limiter.

Claim 8

The interface circuit of claim 6 wherein said receiver further includes signal processing circuitry and said limiter comprises a differential amplifier whose output is coupled to said signal processing circuitry.

Claim 9

The interface circuit of claim 6 wherein said voltage dividing means provides equal weighting to the output signals from said first and second detection means.

Claim 10

The interface circuit of claim 1, wherein said limiter has a signal input terminal and a reference input terminal, said signal input terminal is directly coupled to and receiving output signals from said discriminator and said coupling means comprises voltage dividing means for selectively weighting and averaging the output signals from said first and second detection means to provide a bias reference signal to the reference input terminal of said limiter.

Claim 11

The interface circuit of claim 9 wherein said limiter comprises a differential amplifier.

Claim 12

The interface circuit of claim 9 wherein said voltage dividing means provides equal weighting to the output signals from said first and second detection means.

Claim 13

The interface circuit of claim 9 wherein said first and second detection means further include delay means, responsive to said power switching means, to delay the detection means output signals for a sufficient time to allow the decay of any transients in the discriminator output signals.

Claim 14

A frequency shift keying radio receiver comprising: a receiver circuit containing a plurality of radio frequency elements including a discriminator for the reception and detection of broadcast signals; power switching means coupled to a source of power for periodically supplying power to said radio frequency elements; a limiter directly coupled to said discriminator to limit amplitude variations in a received signal and to produce a limited output signal; first detection means having an input coupled to said discriminator for detecting a peak or maximum signal magnitude and producing an output signal corresponding thereto; second detection means having an input coupled to said discriminator for detecting a valley or minimum signal magnitude and producing an output signal corresponding thereto; said first and second detection means being coupled to said power switching means and said first and second detection means each include means, responsive to said power switching means, for initializing the magnitudes of the corresponding output signals; and averaging means coupling the output signals from said first and second detection means to weigh and average the magnitudes of the output signals in a predetermined manner and supply reference signals to said limiter; whereby said limiter is always biased in accordance with a predetermined averaging of the received and discriminated signals.

Claim 15

A frequency shift keying radio receiver comprising: a receiver circuit containing a plurality of radio frequency elements including a discriminator for the reception and detection of broadcast signals; power switching means coupled to a source of power for periodically supplying power to said radio frequency elements; a limiter directly coupled to said discriminator to limit amplitude variations in a received signal and to produce a limited output signal; first detection means having an input coupled to said discriminator for detecting a peak or maximum signal magnitude and producing an output signal corresponding thereto; second detection means having an input coupled to said discriminator for detecting a valley or minimum signal magnitude and producing an output signal corresponding thereto; said first and second detection means being coupled to said power switching means and said first and second detection means each include means, responsive to said power switching means, for initializing the magnitudes of the corresponding output signals; and averaging means coupling the output signals from said first and second detection means to weigh and average the magnitudes of the output signals in a predetermined manner and supply reference signals to said limiter; whereby said limiter is always biased in accordance with a predetermined averaging of the received and discriminated signals.

Claim 16

The receiver of claim 13 further including signal processing circuitry coupled to the output of said limiter to identify the reception of selective calls.

Claim 17

The receiver of claim 14, wherein said limiter comprises a differential amplifier which has a signal input terminal directly coupled to and receiving output signals from said discriminator and a reference input terminal coupled to said averaging means.

Claim 18

The interface circuit of claim 15 wherein said first and second detection means further include delay means, responsive to said power switching means, to delay the detection means output signals for a sufficient time to allow the decay of any transients in the discriminator output signal.

Claim 19

In a frequency shift keying receiver having a plurality of radio frequency elements including a discriminator which is the last stage of said elements, said receiver including power switching means coupled to a power source for periodically supplying power to said elements, a limiter interface circuit coupled to said discriminator, comprising: a signal limiter directly coupled to said discriminator and receiving output signals therefrom; first detection means having an input coupled to said discriminator for detecting a peak or maximum signal magnitude and producing an output signal corresponding thereto; second detection means having an input coupled to said discriminator for detecting a valley or minimum signal magnitude and producing an output signal corresponding thereto; said first and second detection means being coupled to said power switching means and said first and second detection means each include means, responsive to said power switching means, for initializing the magnitudes of the corresponding output signals; said first and second detection means further including delay means, responsive to said power switching means, to delay the detection means output signals for a sufficient time to allow the decay of any transients in the discriminator output signals; and means coupling the output signals from said first and second detection means to said signal limiter to provide a reference signal thereto.

Claim 20

In a frequency shift keying receiver having a plurality of radio frequency elements including a discriminator which is the last stage of said elements, said receiver including power switching means coupled to a power source for periodically supplying power to said elements, a limiter interface circuit coupled to said discriminator, comprising: a signal limiter directly coupled to said discriminator and receiving output signals therefrom; first detection means having an input coupled to said discriminator for detecting a peak or maximum signal magnitude and producing an output signal corresponding thereto; second detection means having an input coupled to said discriminator for detecting a valley or minimum signal magnitude and producing an output signal corresponding thereto; said first and second detection means being coupled to said power switching means and said first and second detection means each include means, responsive to said power switching means, for initializing the magnitudes of the corresponding output signals; said first and second detection means further including delay means, responsive to said power switching means, to delay the detection means output signals for a sufficient time to allow the decay of any transients in the discriminator output signals; and means coupling the output signals from said first and second detection means to said signal limiter to provide a reference signal thereto.