US3688205A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for the compensation of the direct current voltage disturbance component occurring in the the demodulation of frequency-re-scanned binary data signals
Assignee: Individual
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Filing: 1970-07-30
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Granted: 1972-08-29
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Expires: 1990-07-30
Abstract
Abstract A circuit arrangement for compensation of the direct current disturbance component in the demodulation of frequency modulated binary data signals is described. The discriminator output is coupled to a first input of two difference amplifiers. A limiter at the output of one of the difference amplifiers produces a correct d.c. signal, which signal is coupled to a second input of the other difference amplifier. A timing element couples the output of said other amplifier to a second input of said one difference amplifier.
Inventors
- 👤 Erich Burger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 01:38
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/10; H04L27/14; H04L27/142
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
122 words
Apparatus for compensating for the direct current voltage disturbance component occurring in the output of demodulating means for frequency modulated, binary data signals, comprising: first difference amplifier means having first and second inputs with the output of said demodulating means being direct current coupled to said first input, first limiter means for receiving the output of said first amplifier and for producing therefrom a corrected direct current, demodulated signal, second difference amplifier means havIng first and second inputs, said first input being coupled to the output of said demodulating means and said second input being coupled to the output of said limiter means, and first integrating means coupling the output of said second amplifier to said second input of said first amplifier.
Claim 2
Dependent Claim
122 words
Apparatus for compensating for the direct current voltage disturbance component occurring in the output of demodulating means for frequency modulated, binary data signals, comprising: first difference amplifier means having first and second inputs with the output of said demodulating means being direct current coupled to said first input, first limiter means for receiving the output of said first amplifier and for producing therefrom a corrected direct current, demodulated signal, second difference amplifier means havIng first and second inputs, said first input being coupled to the output of said demodulating means and said second input being coupled to the output of said limiter means, and first integrating means coupling the output of said second amplifier to said second input of said first amplifier.
Claim 3
Dependent Claim
33 words
The apparatus defined in claim 1 wherein said integrating means comprises an RC circuit having a time constant greater than the rise time of a transmitted binary step at the lowest transmission speed.
Claim 4
Dependent Claim
44 words
The apparatus defined in claim 1, further comprising subtraction means having as inputs respectively, the input and output signals of said first limiter means and second integrating means coupling the output of said subtraction means to said second input of said second difference amplifier.
Claim 5
Dependent Claim
98 words
The apparatus defined in claim 1 further comprising: channel separation circuit means for separating one of the messages in duplex, frequency modulated transmissions, said channel separation circuit means having inputs connected, respectively, to the input and output of said limiter means, addition means for receiving said one signal from said channel separation means and the other signal of said duplex transmission from said first limiter means and for producing an output signal coupled to said second input of said second difference amplifier, and second limiter means for producing a correct direct current output from said one separated signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-08-29 | 1976-02-28 | 1976-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-08-29 | 1980-02-28 | 1980-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-08-29 | 1984-02-28 | 1984-08-29 | $7700.00 | Window Closed / Lapsed |