Multi-layered interconnection structure for a semiconductor device

Claim 2

An interconnection layer for a semiconductor device, comprising: a refractory metal silicide layer formed on a surface of a silicon layer; a first refractory metal nitride layer formed on said refractory metal silicide layer by a sputtering process so as to provide said first refractory metal nitride layer with a first crystalline structure; a second refractory metal nitride layer formed on said first refractory metal nitride layer by thermal nitriding process so as to provide said second refractory metal nitride layer with a second crystalline structure which differs from said first crystalline structure of said first refractory metal nitride layer, said second crystalline structure comprising a close packed structure; and a conductor layer on said second refractory metal nitride layer.

Claim 3

An interconnection layer according to claim 1, wherein said first refractory metal nitride layer is formed by a CVD process.

Claim 4

An interconnection layer for a semiconductor, comprising: a refractory metal silicide layer formed on a surface of a semiconductor substrate; a refractory metal nitride first layer formed on said refractory metal silicide layer having a length of grain structure in the direction of thickness of said first layer that is equal to said first layer thickness; a refractory metal nitride second layer formed on said refractory metal nitride first layer having a length of grain structure in the direction of thickness of said second layer that is substantially less than said second layer thickness; and a conductor layer formed on said refractory metal nitride second layer.

Claim 5

An interconnection layer for a semiconductor, comprising: a refractory metal silicide layer formed on a surface of a semiconductor substrate; a refractory metal nitride first layer formed on said refractory metal silicide layer having a length of grain structure in the direction of thickness of said first layer that is equal to said first layer thickness; a refractory metal nitride second layer formed on said refractory metal nitride first layer having a length of grain structure in the direction of thickness of said second layer that is substantially less than said second layer thickness; and a conductor layer formed on said refractory metal nitride second layer.

Claim 6

A semiconductor memory device comprising an interconnected layer having a multi-layered structure, comprising: a first conductivity type of semiconductor substrate having a major surface, a second conductivity type first, second and third impurity regions formed spaced apart from each other by a predetermined space on the major surface of said semiconductor substrate, a gate electrode formed between said first and second impurity regions of the major surface of said semiconductor substrate through a first insulating layer, a first control gate formed between said second and third impurity regions of the major surface of said semiconductor substrate through a second insulating layer, a floating gate formed on a surface of said first control gate through a third insulating layer, a second control gate formed on a surface of said floating gate through a fourth insulating layer, an interconnection layer connected to said first impurity region through a contact hole, said interconnection layer further comprising, a refractory metal silicide layer formed on a surface of said first impurity region; a first refractory metal nitride layer formed on said refractory metal silicide layer by a sputtering process so as to provide said first refractory metal nitride layer with a first crystalline structure; a second refractory metal nitride layer formed on said first refractory metal nitride layer by a thermal nitriding process so as to provide said second refractory metal nitride layer with a second crystalline structure which differs from said first crystalline structure of said first refractory metal nitride layer, said second crystalline structure comprising a close packed structure; and a conductor layer on said second refractory metal nitride layer.

Claim 7

A semiconductor memory device comprising an interconnected layer having a multi-layered structure, comprising: a first conductivity type of semiconductor substrate having a major surface, a second conductivity type first, second and third impurity regions formed spaced apart from each other by a predetermined space on the major surface of said semiconductor substrate, a gate electrode formed between said first and second impurity regions of the major surface of said semiconductor substrate through a first insulating layer, a first control gate formed between said second and third impurity regions of the major surface of said semiconductor substrate through a second insulating layer, a floating gate formed on a surface of said first control gate through a third insulating layer, a second control gate formed on a surface of said floating gate through a fourth insulating layer, an interconnection layer connected to said first impurity region through a contact hole, said interconnection layer further comprising, a refractory metal silicide layer formed on a surface of said first impurity region; a first refractory metal nitride layer formed on said refractory metal silicide layer by a sputtering process so as to provide said first refractory metal nitride layer with a first crystalline structure; a second refractory metal nitride layer formed on said first refractory metal nitride layer by a thermal nitriding process so as to provide said second refractory metal nitride layer with a second crystalline structure which differs from said first crystalline structure of said first refractory metal nitride layer, said second crystalline structure comprising a close packed structure; and a conductor layer on said second refractory metal nitride layer.

Claim 8

A semiconductor memory device according to claim 4, wherein said first refractory metal nitride layer is formed by a CVD process.