Nonvolatile semiconductor memory storage

Abstract

Abstract PURPOSE:To prevent the lowering of the yield of products and eliminate difficulty on the design of a circuit while enabling writing at high speed by providing a small gate with an extent that a capacitance coupling coefficient with a floating gate can be ignored, using the potential of all control gates as grounding potential and applying positive potential only to another gate. CONSTITUTION:A select gate SG is formed separated from a cell. A capacitance coupling coefficient between the SG and an FG is sufficiently smaller than that between a CG1-FG and a CG2-FG. When reading the information of the cell, the CG1 and the CG2 are brought simultaneously to 0V, voltage such as 5V is applied to the SG, and the state of conduction between a drain 1 and a source 2 is observed. Consequently, there is no necessity for writing until the threshold value of the cell reaches 5V or higher, and voltage may be written as the value of voltage such as approximately 0.2-0.3V. When the SG is formed in parallel with the CG1, the SG may be formed by using the same P-1 polycrystalline silicon as the CG1, and the same P-1 polycrystalline silicon as the FG may be used. It may be shaped newly by polycrystalline silicon as another fourth layer.

Inventors

• 👤 Sunao Shibata
• 👤 直 柴田

Bibliographic Details