Anti-noise circuits

Claim 2

An anti-noise circuit for suppressing ground bound and V cc droop in the power rails of an integrated circuit device having an input stage with ground and supply relatively quiet power rails and an output stage with switching output transistor elements and ground and supply output power rails characterized by lead inductance, said output power rails being subject to power rail transient voltage noise upon switching of the output transistor elements, said anti-noise circuit comprising: a power rail noise detector circuit operatively coupled for detecting a transient voltage difference in an output power rail relative to a quiet power rail upon switching of an output transistor element and for generating a transient power rail noise signal (PRNS) during occurrence of the detected transient voltage difference; and a noise control circuit means having an anti-noise transistor element operatively coupled to at least one output detector circuit, said anti-noise transistor element having a control node coupled to receive the PRNS for transient suppression of turn on of said output transistor element during transient occurrence of a PRNS.

Claim 3

The anti-noise circuit of claim 1 wherein the output transistor elements comprise a pullup transistor element and a pulldown transistor element, wherein the power rail noise detector circuit comprises a ground bounce detector circuit generating a transient ground bounce signal (GBS) during transient occurrence of ground bounce in the ground output power rail, and wherein the anti-noise transistor element's control node is coupled to receive the GBS for transient suppression of turn on of the pulldown transistor element during transient occurrence of a GBS.

Claim 4

The anti-noise circuit of claim 1 wherein the output transistor elements comprise a pullup transistor element and a pulldown transistor element, wherein the power rail noise detector circuit comprises a supply droop detector circuit generating a transient supply droop signal (VDS) during transient occurrence of V cc droop in the supply output power rail and wherein the anti-noise transistor element's control node is coupled to receive the VDS for transient suppression of turn on of the pullup transistor element during transient occurrence of a VDS.

Claim 5

The anti-noise circuit of claim 2 wherein the power rail noise detector circuit also comprises a supply droop detector circuit generating a transient supply droop signal (VDS) during transient occurrence of V cc droop in the supply output power rail, and wherein the anti-noise transistor element is also operatively coupled to the pullup transistor element with said control node coupled to receive the VDS for transient suppression of turn on of the pullup transistor element during transient occurrence of a VDS.

Claim 6

An anti-noise circuit for suppressing ground bounce and V cc droop in the power rails of an integrated circuit device having an output stage with switching output transistor elements and ground and supply output power rails characterized by lead inductance, said output power rails being subject to power rail transient voltage noise upon switching of the output transistor elements, said anti-noise circuit comprising: a power rail transient voltage noise detector circuit operatively coupled for detecting a transient voltage drop across the output power rail lead inductance upon switching of an output transistor element and for generating a transient power rail noise signal (PRNS) during occurrence of the detected transient voltage drop; and a noise control circuit means having an anti-noise transistor element operatively coupled to at lest one switching output transistor element of the output stage and to the power rail transistor voltage noise detector circuit, said anti-noise transistor element having a control node coupled to receive the PRNS for transient suppression of turn on of said output transistor element during transient occurrence of a PRNS.

Claim 7

An anti-noise circuit for suppressing ground bounce and V cc droop in the power rails of an integrated circuit device having an output stage with switching output transistor elements and ground and supply output power rails characterized by lead inductance, said output power rails being subject to power rail transient voltage noise upon switching of the output transistor elements, said anti-noise circuit comprising: a power rail transient voltage noise detector circuit operatively coupled for detecting a transient voltage drop across the output power rail lead inductance upon switching of an output transistor element and for generating a transient power rail noise signal (PRNS) during occurrence of the detected transient voltage drop; and a noise control circuit means having an anti-noise transistor element operatively coupled to at lest one switching output transistor element of the output stage and to the power rail transistor voltage noise detector circuit, said anti-noise transistor element having a control node coupled to receive the PRNS for transient suppression of turn on of said output transistor element during transient occurrence of a PRNS.

Claim 8

An anti-ground bounce circuit for a multi-stage circuit having at least one input stage with internal ground line comprising a relatively quiet ground (QG) and at least one output stage with an output ground line comprising an output ground (PG), said internal and output ground lines being relatively isolated, said output stage comprising an input for receiving data signals of high and low potential and an output for delivering data signals, an output pulldown transistor element coupled between the output and output ground PG for sinking current from the output to output ground, and an output pullup transistor element coupled between a power supply current source and the output for sourcing current from high potential to the output, said transistor elements comprising a primary current path and primary current path first and second nodes, and a control node and control circuit for controlling the conducting state of the primary current path, said anti-ground bounce circuit comprising: a ground bounce detector circuit for generating a transient ground bounce signal (GBS) during transient occurrence of ground bounce of potential in the output ground relative to the quiet ground; and an anti-bounce transistor element (ABT) having the primary current path first and second nodes coupled in the control circuit of the output pulldown transistor element; said anti-bounce transistor element comprising a low resistance in its primary current path in a conducting state and a high resistance in a non conducting state, the control node of said anti-bounce transistor element being coupled to the ground bounce detector circuit for transient increase of resistance in the control circuit of the output pulldown transistor element during a transient GBS from the ground bounce detector circuit for transient suppression of turn on of the output pulldown transistor element thereby reducing ground bounce in the output ground.

Claim 9

An anti-ground bounce circuit for a multi-stage circuit having at least one input stage with internal ground line comprising a relatively quiet ground (QG) and at least one output stage with an output ground line comprising an output ground (PG), said internal and output ground lines being relatively isolated, said output stage comprising an input for receiving data signals of high and low potential and an output for delivering data signals, an output pulldown transistor element coupled between the output and output ground PG for sinking current from the output to output ground, and an output pullup transistor element coupled between a power supply current source and the output for sourcing current from high potential to the output, said transistor elements comprising a primary current path and primary current path first and second nodes, and a control node and control circuit for controlling the conducting state of the primary current path, said anti-ground bounce circuit comprising: a ground bounce detector circuit for generating a transient ground bounce signal (GBS) during transient occurrence of ground bounce of potential in the output ground relative to the quiet ground; and an anti-bounce transistor element (ABT) having the primary current path first and second nodes coupled in the control circuit of the output pulldown transistor element; said anti-bounce transistor element comprising a low resistance in its primary current path in a conducting state and a high resistance in a non conducting state, the control node of said anti-bounce transistor element being coupled to the ground bounce detector circuit for transient increase of resistance in the control circuit of the output pulldown transistor element during a transient GBS from the ground bounce detector circuit for transient suppression of turn on of the output pulldown transistor element thereby reducing ground bounce in the output ground.

Claim 10

The anti-ground bounce circuit of claim 6 wherein said transistor elements comprise MOS transistors.

Claim 11

The anti-ground bounce circuit of claim 7 wherein the pulldown transistor element and anti-bounce transistor element comprise NMOS transistor elements.

Claim 12

The anti-ground bounce circuit of claim 7 wherein the pulldown transistor element comprises a PMOS transistor element and the anti-bounce transistor element comprises an NMOS transistor element.

Claim 13

The anti-ground bounce circuit of claim 6 wherein said transistor elements comprise bipolar transistors.

Claim 14

The anti-ground bounce circuit of claim 10 wherein the pulldown transistor element and anti-bounce transistor element comprise NPN transistors.

Claim 15

The anti-ground bounce circuit of claim 6 wherein said output stage comprises first and second current amplification stages, wherein the pulldown transistor element is in the second current amplification stage, and wherein the anti-bounce transistor element is coupled with its primary current path in series between the first amplification stage and the control node of the pulldown transistor element.

Claim 16

The circuit of claim 6 wherein said input stage includes an internal V cc supply line comprising a relatively quiet supply (QV) and said output stage comprises an output V cc supply line comprising an output supply (PV), said internal and output supply lines being relatively isolated, said circuit including an anti V cc droop circuit comprising: a V cc droop detector circuit for generating a transient V cc droop signal (VDS) during transient occurrence of V cc droop in the output supply PV relative to the quiet supply QV; and an anti-droop transistor element (ADT) having first and second primary current path nodes coupled in the control circuit of the output pullup transistor element, said anti-droop transistor element comprising a low resistance in its primary current path in a conducting state and a high resistance in the nonconducting state, the control node of said anti-droop transistor element being coupled to the V cc droop detector circuit for transient increase of resistance in the control circuit of the output pullup transistor element during a transient VDS from the V cc droop detector circuit for transient suppression of turn on of the output pullup transistor element thereby reducing V cc droop in the output supply PV.

Claim 17

The circuit of claim 13 wherein the transistor elements comprise MOS transistors, the pullup transistor element comprises a PMOS transistor, and the anti-droop transistor element comprises an NMOS transistor element.

Claim 18

The circuit of claim 13 wherein the ABT and ADT comprise the same transistor element.

Claim 19

The anti-ground bounce circuit of claim 6 wherein the output stage comprises a tristate device with tristate control transistor elements (TCT), at least one TCT being coupled in the control circuit of the pulldown transistor element and wherein said TCT comprises the ABT.

Claim 20

An anti-V cc droop circuit for a multi-stage circuit having at least one input stage with internal V cc supply line comprising a relatively quiet supply (QV) and at least one output stage with an output V cc supply line comprising an output supply (PV) said internal and output supply lines being relatively isolated, said output stage comprising an input for receiving data signals of high and low potential and an output for delivering data signals, an output pulldown transistor element coupled between the output and ground for sinking current from the output to ground, and an output pullup transistor element coupled between the output supply PV current source and the output for sourcing current from high potential to the output, said transistor elements comprising a primary current path and primary current path first and second nodes, and a control node and control circuit for controlling the conducting state of the primary current path, said anti-V cc droop circuit comprising: a V cc droop detector circuit for generating a transient V cc droop signal (VDS) during transient occurrence of V cc droop in the output supply PV relative to the quiet supply QV; and an anti-droop transistor element having the primary current path first and second nodes coupled in the control circuit of the output pullup transistor element, said antidroop transistor element comprising a low resistance in its primary current path in a conducting state and a high resistance in a nonconducting state, the control node of said anti-droop transistor element being coupled to the V cc droop detector circuit for transient increase of resistance in the control circuit of the output pullup transistor element during a transient VDS from the V cc droop detector circuit for transient suppression of turn on of the output pullup transistor element thereby reducing V cc droop in the output supply PV.

Claim 21

An anti-V cc droop circuit for a multi-stage circuit having at least one input stage with internal V cc supply line comprising a relatively quiet supply (QV) and at least one output stage with an output V cc supply line comprising an output supply (PV) said internal and output supply lines being relatively isolated, said output stage comprising an input for receiving data signals of high and low potential and an output for delivering data signals, an output pulldown transistor element coupled between the output and ground for sinking current from the output to ground, and an output pullup transistor element coupled between the output supply PV current source and the output for sourcing current from high potential to the output, said transistor elements comprising a primary current path and primary current path first and second nodes, and a control node and control circuit for controlling the conducting state of the primary current path, said anti-V cc droop circuit comprising: a V cc droop detector circuit for generating a transient V cc droop signal (VDS) during transient occurrence of V cc droop in the output supply PV relative to the quiet supply QV; and an anti-droop transistor element having the primary current path first and second nodes coupled in the control circuit of the output pullup transistor element, said antidroop transistor element comprising a low resistance in its primary current path in a conducting state and a high resistance in a nonconducting state, the control node of said anti-droop transistor element being coupled to the V cc droop detector circuit for transient increase of resistance in the control circuit of the output pullup transistor element during a transient VDS from the V cc droop detector circuit for transient suppression of turn on of the output pullup transistor element thereby reducing V cc droop in the output supply PV.

Claim 22

The circuit of claim 17 wherein the transistor elements comprise MOS transistors.

Claim 23

The circuit of claim 18 wherein the output pullup transistor element comprises a PMOS transistor element and the anti-droop transistor element comprises an NMOS transistor element.

Claim 24

The circuit of claim 17 wherein said transistor elements comprise bipolar transistors.

Claim 25

The circuit of claim 20 wherein the output pullup transistor element and anti-droop transistor element comprise NPN transistors.

Claim 26

The circuit of claim 17 wherein the output stage comprises first and second current amplification stages, wherein the pullup transistor element is included in the second current amplification stage, and wherein said antidroop transistor element is coupled with the primary current path in series between the first current amplification stage and the control node of said output pullup transistor element.

Claim 27

An anti-ground noise circuit for a multi-stage circuit having at least one input stage with internal ground line comprising a relatively quiet ground (QG) and at least one output stage with an output ground line comprising an output ground (PG), said internal and output ground lines being relatively isolated, said output stage comprising an input for receiving data signals of high and low potential and an output for delivering data signals, an output pulldown transistor element coupled between the output and output ground for sinking current from the output to output ground, said transistor elements comprising a primary current path and primary current path first and second nodes, and a control node and control node circuit for controlling the conducting state of the primary current path, said antiground noise circuit comprising: a ground noise detector circuit for generating a transient ground noise signal (GNS) during transient occurrence of ground noise in the output ground relative to the quiet ground in excess of a selected threshold level; and an anti-noise transistor element (ANT) having the primary current path first and second nodes coupled in the control circuit of the output pulldown transistor element, the control node of said anti-noise transistor element being coupled to the ground noise detector circuit for transient change of conducting state of the primary current path of the output pulldown transistor element during a transient GNS from the ground noise detector circuit for transient suppression of turn on of the output pulldown transistor element thereby reducing ground noise in the output ground; and an ANT control circuit operatively coupled to the ANT control node and the ground noise detector circuit for further controlling the conducting state of the ANT primary current path in response to the logic condition of the output stage, said ANT control circuit comprising a data input condition transistor element (ICT2) for conditioning control of said ANT according to the data signal at the input to the output stage.

Claim 28

An anti-ground noise circuit for a multi-stage circuit having at least one input stage with internal ground line comprising a relatively quiet ground (QG) and at least one output stage with an output ground line comprising an output ground (PG), said internal and output ground lines being relatively isolated, said output stage comprising an input for receiving data signals of high and low potential and an output for delivering data signals, an output pulldown transistor element coupled between the output and output ground for sinking current from the output to output ground, said transistor elements comprising a primary current path and primary current path first and second nodes, and a control node and control node circuit for controlling the conducting state of the primary current path, said antiground noise circuit comprising: a ground noise detector circuit for generating a transient ground noise signal (GNS) during transient occurrence of ground noise in the output ground relative to the quiet ground in excess of a selected threshold level; and an anti-noise transistor element (ANT) having the primary current path first and second nodes coupled in the control circuit of the output pulldown transistor element, the control node of said anti-noise transistor element being coupled to the ground noise detector circuit for transient change of conducting state of the primary current path of the output pulldown transistor element during a transient GNS from the ground noise detector circuit for transient suppression of turn on of the output pulldown transistor element thereby reducing ground noise in the output ground; and an ANT control circuit operatively coupled to the ANT control node and the ground noise detector circuit for further controlling the conducting state of the ANT primary current path in response to the logic condition of the output stage, said ANT control circuit comprising a data input condition transistor element (ICT2) for conditioning control of said ANT according to the data signal at the input to the output stage.

Claim 29

The anti-ground noise circuit of claim 23 wherein the output stage is a tristate device with tristate output enable signal OE and wherein the ANT control circuit further comprises an output enable condition transistor (OECT2) for conditioning control of said ANT according to the state of the OE signal and wherein the tristate device comprises tristate control transistor elements (TCT) for disabling the pulldown transistor element in the high impedance third state, said ANT comprising at least one TCT.

Claim 30

An anti-noise circuit for dissipating parasitic tank circuit energy causing ground undershoot and V cc overshoot in the power rails of an integrated circuit device having an output stage with switching output transistor elements and ground and supply output power rails characterized by lead inductance, said output power rails being subject to power rail transient voltage noise upon switching of the output transistor elements comprising: a current source for sourcing a transient sacrificial current flow; an anti-noise circuit transistor element (AUCT, AOCT, AUCT1, AUCT2) separate from the switching output transistor elements having a primary current path and selected resistance in the primary current path providing dissipating resistance means, said anti-noise circuit transistor element having a control node for controlling the conducting state of the anti-noise circuit transistor element; said anti-noise circuit coupling the current source, said anti-noise circuit transistor element with dissipating resistance means, and said power rail lead inductance in series in a sacrificial current path; and control circuit means coupled to the control node of the anti-noise circuit transistor element for causing a transient sacrificial current flow in the sacrificial current path following switching of an output transistor element for dissipating parasitic tank circuit energy in said dissipating resistance means.

Claim 31

An anti-noise circuit for dissipating parasitic tank circuit energy causing ground undershoot and V cc overshoot in the power rails of an integrated circuit device having an output stage with switching output transistor elements and ground and supply output power rails characterized by lead inductance, said output power rails being subject to power rail transient voltage noise upon switching of the output transistor elements comprising: a current source for sourcing a transient sacrificial current flow; an anti-noise circuit transistor element (AUCT, AOCT, AUCT1, AUCT2) separate from the switching output transistor elements having a primary current path and selected resistance in the primary current path providing dissipating resistance means, said anti-noise circuit transistor element having a control node for controlling the conducting state of the anti-noise circuit transistor element; said anti-noise circuit coupling the current source, said anti-noise circuit transistor element with dissipating resistance means, and said power rail lead inductance in series in a sacrificial current path; and control circuit means coupled to the control node of the anti-noise circuit transistor element for causing a transient sacrificial current flow in the sacrificial current path following switching of an output transistor element for dissipating parasitic tank circuit energy in said dissipating resistance means.

Claim 32

The anti-noise circuit of claim 25 wherein the switching output transistor elements comprise a pullup transistor element and a pulldown transistor element, wherein the anti-noise circuit couples the current source, anti-noise circuit transistor element with dissipating resistance means (AUCT, AUCT1, AUCT), and ground output power rail lead inductance in series in a sacrificial current path, and wherein the control circuit means is coupled to cause a transient sacrificial current flow in the sacrificial current path following switching of an output transistor element for dissipating parasitic ground undershoot energy from the ground output power rail in the dissipating resistance means.

Claim 33

The anti-noise circuit of claim 25 wherein the switching output transistor elements comprise a pullup transistor element and a pulldown transistor element, wherein the anti-noise circuit coupled the current source, anti-noise circuit transistor element with dissipating resistance means (AOCT), and supply output power rail lead inductance in series in the sacrificial current path, and wherein the control circuit means is coupled to cause transient sacrificial current flow in the sacrificial current path following switching of an output transistor element for dissipating parasitic V cc overshoot energy from the supply output power rail in the dissipating resistance means.

Claim 34

The anti-noise circuit of claim 25 wherein the control circuit means comprises a power rail noise detector circuit operatively coupled for detecting a transient voltage noise in a power rail and for generating a transient power rail noise signal (PRNS) during occurrence of the detected transient voltage noise, said PRNS being coupled by the control circuit means to a control node of the anti-noise circuit transistor element to cause transient sacrificial current flow in the sacrificial current path.

Claim 35

An anti-undershoot circuit for an integrated circuit having at least one output stage with an output ground lead comprising an output ground (PG), and an output supply lead comprising an output supply (PV), said output stage comprising an input for receiving data signals of high and low potential and an output for delivering data signals, an output pulldown transistor element coupled between the output and output ground PG for sinking current from the output to output ground, and an output pullup transistor element coupled between the output supply PV and the output for sourcing current from the output supply to the output, said transistor elements each comprising a primary current path and primary current path first and second nodes, and a control node and control circuit for controlling the conducting state of the primary current path, said output ground being subject to ground noise including ground undershoot of potential due to output ground lead inductance during transition from high to low potential at the output, said anti-undershoot circuit comprising: an anti-undershoot circuit transistor element (AUCT) having the primary current path first and second nodes coupled in an anti-undershoot circuit, said anti-undershoot circuit comprising the current source, the primary current path of the AUCT, and said output ground lead inductance coupled in series; an AUCT control circuit coupled to the control node of the AUCT for establishing transient flow of a sacrificial current from said current source through the AUCT primary current path and through the output ground lead inductance, said AUCT comprising selected resistance in the primary current path in he conducting state for dissipating undershoot electrical energy from the output ground lead inductance thereby damping ground undershoot of potential in the output ground.

Claim 36

An anti-undershoot circuit for an integrated circuit having at least one output stage with an output ground lead comprising an output ground (PG), and an output supply lead comprising an output supply (PV), said output stage comprising an input for receiving data signals of high and low potential and an output for delivering data signals, an output pulldown transistor element coupled between the output and output ground PG for sinking current from the output to output ground, and an output pullup transistor element coupled between the output supply PV and the output for sourcing current from the output supply to the output, said transistor elements each comprising a primary current path and primary current path first and second nodes, and a control node and control circuit for controlling the conducting state of the primary current path, said output ground being subject to ground noise including ground undershoot of potential due to output ground lead inductance during transition from high to low potential at the output, said anti-undershoot circuit comprising: an anti-undershoot circuit transistor element (AUCT) having the primary current path first and second nodes coupled in an anti-undershoot circuit, said anti-undershoot circuit comprising the current source, the primary current path of the AUCT, and said output ground lead inductance coupled in series; an AUCT control circuit coupled to the control node of the AUCT for establishing transient flow of a sacrificial current from said current source through the AUCT primary current path and through the output ground lead inductance, said AUCT comprising selected resistance in the primary current path in he conducting state for dissipating undershoot electrical energy from the output ground lead inductance thereby damping ground undershoot of potential in the output ground.

Claim 37

The anti-undershoot circuit of claim 29 wherein the AUCT control circuit comprises: an undershoot detector circuit generating a transient ground undershoot signal (GUS) during transient occurrence of undershoot of potential in the output ground said GUS being coupled to the AUCT control node for causing transient flow of sacrificial current through the selected resistance of the AUCT primary current path and said output ground lead inductance, for dissipating undershoot electrical energy stored in the output ground lead inductance.

Claim 38

The anti-undershoot circuit of claim 29 wherein the integrated circuit comprises an input stage with input ground lead comprising a relatively quiet ground QG and wherein the control node of the AUCT is coupled to and QG whereby the AUCT also functions as a ground undershoot detector circuit generating a transient ground undershoot signal (GUS) at the AUCT control node during transient occurrence of undershoot of potential in the output ground PG for causing the transient sacrificial current flow.

Claim 39

The anti-undershoot circuit of claim 29 wherein the anti-undershoot circuit is coupled between the output supply PV and output ground PG through the output of said output stage, wherein the primary current path first and second nodes of the AUCT are coupled in parallel with the primary current path first and second nodes of the pullup transistor element, and further comprising an anti-undershoot control path resistance element (CPR) coupled in the control circuit of the AUCT, said AUCT control circuit being coupled to the control node of the pullup transistor element through said CPR, sand CPR retarding turn off of the AUCT following transition from high to low potential at the output thereby establishing the transient sacrificial current flow through the primary current path resistance of the AUCT and the output ground lead inductance for dissipation of undershoot electrical energy stored in the output ground lead inductance.

Claim 40

The anti-undershoot circuit of claim 29 wherein the respective primary current path first nodes of the AUCT and pullup transistor element are coupled to the output supply PV, the respective primary current path second nodes of the AUCT and pullup transistor element are coupled to the output of said output stage, and the control node of the AUCT is coupled to the control node of the pullup transistor element through a control path resistance element (CPR) for retarding turn off of the AUCT thereby establishing the transient sacrificial current flow.

Claim 41

The anti-undershoot circuit of claim 33 further comprising: an anti-undershoot switch transistor element (AUST) having the primary current path first and second nodes coupled in series with the CPR, and an undershoot detector circuit, generating a transient ground undershoot signal (GUS) during occurrence of transient undershoot of potential in the output ground; said GUS being coupled to the control node of the AUST for further retarding turn off of the AUCT following transition from high t low potential at the output thereby prolonging said transient flow of sacrificial current through the resistance of the AUCT primary current path and output ground lead inductance for further dissipating undershoot electrical energy stored in the output ground lead inductance.

Claim 42

The anti-undershoot circuit of claim 29 wherein the AUCT control circuit comprises an anti-undershoot control path resistance element (CPR) coupled between the output supply PV and the control node of the AUCT for sourcing current to the control node of the AUCT through said CPR resistance element, and a logic condition transistor element having the primary current path operatively coupled to the control node of the AUCT, the control node of said logic condition transistor element being operatively coupled to said output stage for conditioning and controlling the conducting state of the AUCT in response to the logic condition of the output stage, said CPR retarding turn off of the AUCT following transition from high to low potential at the output thereby establishing the transient sacrificial current flow through the dissipating selected resistance of the primary current path of the AUCT and the power ground lead inductance for dissipating undershoot electrical energy stored in the output ground lead inductance.

Claim 43

The anti-undershoot circuit of claim 35 further comprising: an anti-undershoot switch transistor element (AUST) having the primary current path first and second nodes coupled in series with the CPR resistor element; and an undershoot detector circuit generating a transient ground undershoot signal (GUS) during occurrence of transient undershoot of potential in the output ground; said GUS being operatively coupled to the control node of the AUST for further delaying turn off of the AUCT during occurrence of transient undershoot of potential in the output ground upon transition from high to low potential at the output thereby prolonging the transient flow of sacrificial current through the dissipating selected resistance of the AUCT primary current path, and the output ground lead inductance, for dissipating undershoot electrical energy stored in the output ground lead inductance.

Claim 44

The anti-undershoot circuit of claim 29 wherein the transistor elements comprise MOS transistor elements.

Claim 45

The anti-undershoot circuit of claim 29 wherein said transistor elements comprise bipolar transistor elements.

Claim 46

An anti-undershoot circuit for a multi-stage circuit having an output stage with output ground lead providing an output ground (PG) and output supply lead providing an output supply (PV), said output ground lead being characterized by ground lead inductance, said output stage comprising an input for receiving data signals of high and low potential, an output for delivering data signals, an output pulldown transistor element coupled between the output and output ground PG for sinking current from the output to output ground, and an output pullup transistor element coupled between the output supply PV and the output for sourcing current from the output supply to the output, said transistor elements each comprising a primary current path and primary current path first and second nodes, and a control node for controlling the conducting state of the primary current path, said output ground PG being subject to ground noise including ground potential undershoot due to ground lead inductance during transition from high to low potential at the output, said antiundershoot circuit comprising: an anti-undershoot circuit transistor element (AUCT) having the primary current path first and second nodes operatively coupled in an anti-undershoot circuit, said AUCT being constructed and arranged with selected resistance in the primary current path for dissipating sacrificial current, said anti-undershoot circuit comprising the output supply PV, said AUCT primary current path and primary current path selected resistance, and said output ground PG and output ground lead inductance all coupled in series; and an AUCT control circuit coupled to the AUCT control node for controlling the conducting state of the AUCT, said AUCT control circuit being constructed to establish through the primary current path of the AUCT a transient sacrificial current flow in the anti-undershoot circuit from the output supply PV, through the AUCT primary current path and primary current path selected resistance, and through the output ground lead inductance, following transition from high to low potential at the output, for dissipating undershoot electrical energy stored in the output ground lead inductance; said AUCT control circuit comprising an anti-undershoot control path resistance element (CPR) coupled between the output supply and the AUCT control node for retarding turn off of the AUCT to establish said transient sacrificial current, and at least one logic condition transistor operatively coupled for controlling the conducting state of the AUCT in accordance with the logic condition of the output stage.

Claim 47

An anti-undershoot circuit for a multi-stage circuit having an output stage with output ground lead providing an output ground (PG) and output supply lead providing an output supply (PV), said output ground lead being characterized by ground lead inductance, said output stage comprising an input for receiving data signals of high and low potential, an output for delivering data signals, an output pulldown transistor element coupled between the output and output ground PG for sinking current from the output to output ground, and an output pullup transistor element coupled between the output supply PV and the output for sourcing current from the output supply to the output, said transistor elements each comprising a primary current path and primary current path first and second nodes, and a control node for controlling the conducting state of the primary current path, said output ground PG being subject to ground noise including ground potential undershoot due to ground lead inductance during transition from high to low potential at the output, said antiundershoot circuit comprising: an anti-undershoot circuit transistor element (AUCT) having the primary current path first and second nodes operatively coupled in an anti-undershoot circuit, said AUCT being constructed and arranged with selected resistance in the primary current path for dissipating sacrificial current, said anti-undershoot circuit comprising the output supply PV, said AUCT primary current path and primary current path selected resistance, and said output ground PG and output ground lead inductance all coupled in series; and an AUCT control circuit coupled to the AUCT control node for controlling the conducting state of the AUCT, said AUCT control circuit being constructed to establish through the primary current path of the AUCT a transient sacrificial current flow in the anti-undershoot circuit from the output supply PV, through the AUCT primary current path and primary current path selected resistance, and through the output ground lead inductance, following transition from high to low potential at the output, for dissipating undershoot electrical energy stored in the output ground lead inductance; said AUCT control circuit comprising an anti-undershoot control path resistance element (CPR) coupled between the output supply and the AUCT control node for retarding turn off of the AUCT to establish said transient sacrificial current, and at least one logic condition transistor operatively coupled for controlling the conducting state of the AUCT in accordance with the logic condition of the output stage.

Claim 48

The anti-undershoot circuit of claim 39 wherein the AUCT is coupled at the primary current path second node to output ground through the output of said output stage.

Claim 49

The anti-undershoot of claim 39 wherein the AUCT control circuit comprises a plurality of logic condition transistor elements including a data input condition transistor ICT and an output condition transistor OCT operatively coupled with the respective primary current paths in series between the AUCT control node and output ground, said output supply being coupled to the AUCT control node through the CPR resistance element, said ICT being conditioned by the signal at the input of the output stage and said OCT being conditioned by the signal at the output of the output stage to control transient conduction through the primary current path of the AUCT associated with transition from high to low potential at the output for establishing the transient sacrificial current in the anti-undershoot circuit from the output supply, through the AUCT primary current path and primary current path selected resistance, and through the output ground lead inductance, for dissipating electrical energy stored in the power ground lead inductance.

Claim 50

The anti-undershoot circuit of claim 39 further comprising an anti-undershoot switch transistor (AUST), said AUST primary current path first and second nodes being coupled in series with the CPR resistance element between the power supply current source and AUCT control node, and further comprising a ground undershoot detector circuit generating a transient ground undershoot signal (GUS) during occurrence of transient undershoot of potential in the output ground, said GUS being coupled to the control node of the AUST for retarding turn off of the transient flow of sacrificial current through the primary current path selected resistance of the AUCT, and through the output ground lead inductance, following transition from high to low potential at the output, for further dissipating electrical energy stored in the output ground lead inductance.

Claim 51

The anti-undershoot circuit of claim 41 further comprising an output network operatively coupled between the output and control node oft he OCT for conditioning propagation of an output condition signal to the control node of the OCT for effecting a slow rise in the sacrificial current during turn on of the AUCT to reduce interference in the output supply PV by the current requirements of the AUCT.

Claim 52

The anti-undershoot circuit of claim 39 wherein the output stage comprises a tristate output device with output enable (OE) signal and wherein the AUCT control circuit further comprises an output enable condition transistor element (OECT) operatively coupled to the AUCT control circuit for disabling the AUCT in the high impedance third state of the tristate output device.

Claim 53

A low noise circuit for a multi-stage circuit having at least one input stage with internal ground lead comprising a relatively quiet ground (QG) and at least one output stage with an output ground lead comprising an output ground (PG) and an output supply lead comprising an output supply (PV), said internal and output ground leads having lead inductance and being relatively isolated for coupling to an external ground, said output stage comprising an input for receiving data signals of high and low potential and an output for delivering data signals, an output pulldown transistor element coupled between the output and output ground for sinking current from the output to output ground, and an output pullup transistor element coupled between output supply and the output for sourcing current from the output supply to the output, said transistor elements each comprising a primary current path with primary current path first and second nodes, and a control node and control circuit for controlling the conducting state of the primary current path, said low noise circuit comprising: an anti-undershoot circuit including an anti-undershoot circuit transistor element (AUCT) having the primary current path first and second nodes coupled in the anti-undershoot circuit, said AUCT being characterized by selected resistance in the primary current path in the conducting state providing dissipating resistance means, said anti-undershoot circuit defining a sacrificial current path by coupling the output supply, the AUCT primary current path and selected resistance, and said output ground lead inductance in series; an AUCT control circuit operatively coupled to the control node of the AUCT and constructed for establishing a transient sacrificial current in the anti-undershoot circuit following transition from high to low potential at the output for dissipating undershoot electrical energy stored in the output ground lead inductance in said dissipating resistance means; a ground bounce detector circuit for generating a transient ground bounce signal (GBS) during transient occurrence of ground bounce of potential in the power ground relative to the quiet ground; an anti-bounce transistor element (ABT) having the primary current path first and second nodes coupled in the control circuit of the output pulldown transistor element, said ABT having a low resistance in its primary current path in a conducting state and a high resistance in a non-conducting state; and an ABT control circuit including said ground bounce detector circuit operatively coupled to the control node of the ABT and constructed and arranged to cause transient increase of resistance in the control circuit of the output pulldown transistor element during a transient GBS from the ground bounce detector circuit for transient suppression of turn on of the output pulldown transistor element thereby suppressing ground bounce in the output ground.

Claim 54

A low noise circuit for a multi-stage circuit having at least one input stage with internal ground lead comprising a relatively quiet ground (QG) and at least one output stage with an output ground lead comprising an output ground (PG) and an output supply lead comprising an output supply (PV), said internal and output ground leads having lead inductance and being relatively isolated for coupling to an external ground, said output stage comprising an input for receiving data signals of high and low potential and an output for delivering data signals, an output pulldown transistor element coupled between the output and output ground for sinking current from the output to output ground, and an output pullup transistor element coupled between output supply and the output for sourcing current from the output supply to the output, said transistor elements each comprising a primary current path with primary current path first and second nodes, and a control node and control circuit for controlling the conducting state of the primary current path, said low noise circuit comprising: an anti-undershoot circuit including an anti-undershoot circuit transistor element (AUCT) having the primary current path first and second nodes coupled in the anti-undershoot circuit, said AUCT being characterized by selected resistance in the primary current path in the conducting state providing dissipating resistance means, said anti-undershoot circuit defining a sacrificial current path by coupling the output supply, the AUCT primary current path and selected resistance, and said output ground lead inductance in series; an AUCT control circuit operatively coupled to the control node of the AUCT and constructed for establishing a transient sacrificial current in the anti-undershoot circuit following transition from high to low potential at the output for dissipating undershoot electrical energy stored in the output ground lead inductance in said dissipating resistance means; a ground bounce detector circuit for generating a transient ground bounce signal (GBS) during transient occurrence of ground bounce of potential in the power ground relative to the quiet ground; an anti-bounce transistor element (ABT) having the primary current path first and second nodes coupled in the control circuit of the output pulldown transistor element, said ABT having a low resistance in its primary current path in a conducting state and a high resistance in a non-conducting state; and an ABT control circuit including said ground bounce detector circuit operatively coupled to the control node of the ABT and constructed and arranged to cause transient increase of resistance in the control circuit of the output pulldown transistor element during a transient GBS from the ground bounce detector circuit for transient suppression of turn on of the output pulldown transistor element thereby suppressing ground bounce in the output ground.

Claim 55

The low noise circuit of claim 45 wherein the AUCT control circuit comprises a plurality of logic condition transistors for controlling the AUCT primary current path conducting state in response to the logic condition of said output stage.

Claim 56

The low noise circuit of claim 46 wherein the logic condition transistors include a data input condition transistor (ICT) and a data output condition transistor (OCT) operatively coupled to enable transient conductance by the AUCT upon transition from high to low potential at the output, said input condition transistor ICT and output condition transistor OCT being coupled with their respective primary current paths in series between the AUCT control node and output of the output stage.

Claim 57

The low noise circuit of claim 45 wherein the AUCT control circuit comprises an anti-undershoot control path resistance element (CPR) coupled between the output supply and said AUCT control node for delaying turn off of the AUCT and enabling a transient sacrificial flow of current in the anti-undershoot circuit following transition from high to low potential at the output.

Claim 58

The low noise circuit of claim 48 further comprising: a ground undershoot detector circuit for generating a transient ground undershoot signal (GUS) during transient occurrence of ground undershoot of potential in the power ground relative to the quiet ground; and an anti-undershoot switch transistor element (AUST) operatively coupled with the primary current path in series with said CPR resistance element between the output supply and AUCT control node, the control node of said AUST being coupled to the ground undershoot detector circuit for further delaying turn off of the AUCT and extending transient sacrificial current flow in the anti-undershoot circuit during a transient GUS from the ground undershoot detector circuit for further dissipation of undershoot electrical energy from the output ground lead inductance in the resistance of the AUCT.

Claim 59

The low noise circuit of claim 45 wherein the ABT control circuit comprises at least one logic condition transistor for controlling the conducting state of the ABT in response to a logic condition of the output stage.

Claim 60

The low noise circuit of claim 50 wherein a logic condition transistor of the ABT control circuit comprises a data input condition transistor (ICT2) having the primary current path coupled to the control node of the ABT for conditioning control of the conducting state of the ABT primary current path in response to the data signal at the input of the output stage.

Claim 61

The low noise circuit of claim 51 wherein the output stage comprises a tristate device with a tristate output enable (OE) signal and wherein a further logic condition transistor of the ABT control circuit includes an output enable condition transistor (OECT2) having the primary current path coupled to the control node of the ABT for conditioning control of the conducting state of the ABT primary current path in response to the condition of the tristate device OE signal.

Claim 62

The low noise circuit of claim 45 wherein the output stage comprises a tristate output device with output enable (OE) signal and tristate control transistor elements (TCT's) with at least one TCT being coupled in the control circuit of the pulldown transistor element for disabling the pulldown transistor element during the tristate condition, and wherein said at least one TCT also comprises the ABT.

Claim 63

An anti-overshoot circuit for a multi-stage circuit having an output stage with an output V cc supply lead comprising an output supply (PV) said output supply lead having lead inductance said output stage comprising an input for receiving data signals of high and low potential and an output for delivering data signals, an output pulldown transistor element coupled between the output and ground for sinking current from the output to ground, and an output pullup transistor element coupled between the output supply (PV) and the output for sourcing current from the output supply to the output, said transistor elements comprising a primary current path and primary current path first and second nodes, and a control node and control circuit for controlling the conducting state of the primary current path, said anti-overshoot circuit comprising: an anti-overshoot circuit transistor element (AOCT) having the primary current path first and second nodes coupled in an antiovershoot circuit, said anti-overshoot circuit coupling the output supply PV, primary current path of the AOCT, ground, and output supply lead inductance in series; an AOCT control circuit coupled to the control node of the AOCT for establishing transient flow of a sacrificial current through the AOCT primary current path from said output supply PV and through the output supply lead inductance, said AOCT comprising selected resistance in the primary current path in the conducting state providing dissipating resistance means for dissipating overshoot electrical energy stored in the output supply PV lead inductance.

Claim 64

An anti-overshoot circuit for a multi-stage circuit having an output stage with an output V cc supply lead comprising an output supply (PV) said output supply lead having lead inductance said output stage comprising an input for receiving data signals of high and low potential and an output for delivering data signals, an output pulldown transistor element coupled between the output and ground for sinking current from the output to ground, and an output pullup transistor element coupled between the output supply (PV) and the output for sourcing current from the output supply to the output, said transistor elements comprising a primary current path and primary current path first and second nodes, and a control node and control circuit for controlling the conducting state of the primary current path, said anti-overshoot circuit comprising: an anti-overshoot circuit transistor element (AOCT) having the primary current path first and second nodes coupled in an antiovershoot circuit, said anti-overshoot circuit coupling the output supply PV, primary current path of the AOCT, ground, and output supply lead inductance in series; an AOCT control circuit coupled to the control node of the AOCT for establishing transient flow of a sacrificial current through the AOCT primary current path from said output supply PV and through the output supply lead inductance, said AOCT comprising selected resistance in the primary current path in the conducting state providing dissipating resistance means for dissipating overshoot electrical energy stored in the output supply PV lead inductance.

Claim 65

The anti-overshoot circuit of claim 54 wherein the AOCT control circuit comprises: an overshoot detector circuit generating a transient V cc overshoot signal (VOS) during transient occurrence of overshoot of potential in the output supply PV, said VOS being couple d by the AOCT control circuit to the control node of the AOCT for causing transient flow of sacrificial current through the selected resistance of the AOCT primary current path and output supply lead inductance, for damping and dissipating the overshoot electrical energy from the output supply PV lead inductance.

Claim 66

The anti-overshoot circuit of claim 54 wherein the control node of the AOCT is coupled to a relatively quiet reference supply whereby the AOCT also functions as an overshoot detector circuit generating a transient V cc overshoot signal (VOS) at its own AOCT control node during transient occurrence of overshoot of potential in the output supply PV relative to the quiet reference supply.

Claim 67

A ground noise detector circuit for a multi-stage circuit having at least one input stage with internal ground line comprising a relatively quiet ground (QG) and at least one output stage with an output ground line comprising an output ground (PG) said internal and output ground lines being relatively isolated, said output stage comprising an output for delivering data signals of high and low potential, said output ground being subject to ground noise including ground bounce and ground undershoot during transition from high to low potential at the output, said ground noise detector circuit comprising: a ground noise detector transistor element having primary current path first and second nodes defining the transistor element primary current path, and a control node for controlling the conducting state of the primary current path, power supply circuit means coupled to said first node, said control node being coupled to one of the quiet ground and output ground, and said second node of the primary current path being coupled to the other of the quiet ground and output ground for generating at the first node of the primary current path a transient ground noise signal (GNS) during transient occurrence of ground potential differential between the quiet ground and output ground causing transient change in the conducting state of the primary current path of the ground noise detector transistor element.

Claim 68

A ground noise detector circuit for a multi-stage circuit having at least one input stage with internal ground line comprising a relatively quiet ground (QG) and at least one output stage with an output ground line comprising an output ground (PG) said internal and output ground lines being relatively isolated, said output stage comprising an output for delivering data signals of high and low potential, said output ground being subject to ground noise including ground bounce and ground undershoot during transition from high to low potential at the output, said ground noise detector circuit comprising: a ground noise detector transistor element having primary current path first and second nodes defining the transistor element primary current path, and a control node for controlling the conducting state of the primary current path, power supply circuit means coupled to said first node, said control node being coupled to one of the quiet ground and output ground, and said second node of the primary current path being coupled to the other of the quiet ground and output ground for generating at the first node of the primary current path a transient ground noise signal (GNS) during transient occurrence of ground potential differential between the quiet ground and output ground causing transient change in the conducting state of the primary current path of the ground noise detector transistor element.

Claim 69

The ground noise detector circuit of claim 57 wherein the ground noise detector transistor element comprises a ground bounce detector (GBD) transistor element, wherein said control node is coupled to the output ground and the second node of the primary current path is coupled to the quiet ground for generating at the first node of the primary current path a transient ground bounce signal (GBS) during transient occurrence of ground bounce of potential in the output ground relative to the quiet ground causing transient change in the conducting state of the primary current path of the GBD transistor element.

Claim 70

The ground noise detector circuit of claim 58 wherein the GBD transistor element is an MOS transistor element.

Claim 71

The ground nose detector circuit of claim 58 wherein the GBD transistor element is a bipolar transistor element.

Claim 72

The ground noise detector circuit of claim 59 wherein the GBD MOS transistor element is an NMOS transistor element, and wherein the first node is the drain node, the second node the source node, and control node the gate node.

Claim 73

The ground noise detector circuit of claim 60 wherein the GBD bipolar transistor element is an NPN transistor element, and wherein the first node is the collector node, the second node is the emitter node, and control node the base node.

Claim 74

The ground noise detector circuit of claim 58 further comprising a noninverting stage of current amplification coupled to receive the transient GBS and wherein the ground noise detector circuit delivers a final transient GBS of low potential during transient occurrence of ground bounce of potential in the output ground.

Claim 75

The ground noise detector circuit of claim 58 further comprising an inverting stage of current amplification coupled to receive the transient GBS and wherein the ground noise detector circuit delivers a final transient GBS of high potential during transient occurrence of ground bounce of potential in the output ground.

Claim 76

The ground noise detector circuit of claim 61 wherein the power supply circuit means coupled to said first pin of the GBS NMOS transistor element comprises a PMOS transistor element coupled between said first pin of the NMOS transistor element and a V cc power supply.

Claim 77

The ground noise circuit of claim 57 wherein the ground noise detector transistor element comprises a ground undershoot detector (GUD) transistor element, wherein said control node is coupled to quiet ground, and said second node of the primary current path is coupled to output ground for generating at the first node of the primary current path a transient ground undershoot signal (GUS) during transient occurrence of ground undershoot of potential in the output ground relative to the quiet ground causing transient change in the conducting state of the primary current path of the GUD transistor element.

Claim 78

The ground noise detector circuit of claim 66 wherein the GUD transistor element is an NMOS transistor and wherein the first node is the drain node, second node the source node, and control node the gate node.

Claim 79

The ground noise detector circuit of claim 66 wherein the GUD transistor element is a bipolar NPN transistor, wherein the first node is the collector node, the second node is the emitter node, and control node the base node.

Claim 80

The ground noise detector circuit of claim 66 further comprising an inverting stage of current amplification coupled to receive the transient GUS and wherein the ground noise detector circuit delivers a final transient GUS of high potential during transient occurrence of ground undershoot of potential in the output ground.

Claim 81

The ground noise detector circuit of claim 67 wherein the power supply circuit means coupled to the first pin of the GUD transistor element comprises a PMOS transistor coupled between said first node and a V cc power supply.

Claim 82

A ground bounce detector (GBD) circuit for a multistage circuit having at least one input stage with internal ground line comprising a relatively quiet ground (QG) and at least one output stage with an output ground line comprising an output ground (PG), said internal and output ground lines being relatively isolated, said output stage comprising an output for delivering data signals of high and low potential, said output ground being subject to ground bounce of potential during transition from high to low potential at the output, said ground bounce detector circuit comprising: a ground bounce detector (GBD) transistor element having primary current path first and second nodes defining the transistor element primary current path, and a control node for controlling the conducting state of the primary current path, power supply circuit means coupled to said first node, said control node being coupled to output ground, and said second node of the primary current path being coupled to quiet ground for generating at the first node of the primary current path a transient ground bounce signal (GBS) during transient occurrence of ground bounce of potential in the output ground relative to the quiet ground causing transient change in the conducting state of the primary current path of the GBD transistor element.

Claim 83

A ground bounce detector (GBD) circuit for a multistage circuit having at least one input stage with internal ground line comprising a relatively quiet ground (QG) and at least one output stage with an output ground line comprising an output ground (PG), said internal and output ground lines being relatively isolated, said output stage comprising an output for delivering data signals of high and low potential, said output ground being subject to ground bounce of potential during transition from high to low potential at the output, said ground bounce detector circuit comprising: a ground bounce detector (GBD) transistor element having primary current path first and second nodes defining the transistor element primary current path, and a control node for controlling the conducting state of the primary current path, power supply circuit means coupled to said first node, said control node being coupled to output ground, and said second node of the primary current path being coupled to quiet ground for generating at the first node of the primary current path a transient ground bounce signal (GBS) during transient occurrence of ground bounce of potential in the output ground relative to the quiet ground causing transient change in the conducting state of the primary current path of the GBD transistor element.

Claim 84

The ground bounce detector circuit of claim 71 further comprising a stage of current amplification coupled to receive the GBS.

Claim 85

The ground bounce detector circuit of claim 72 wherein the stage of current amplification comprises a noninverting stage of current amplification and wherein the GBD circuit delivers a transient GBS of low potential during transient occurrence of ground bounce of potential in the output ground.

Claim 86

A ground undershoot detector (GUD) circuit for a multistage circuit having at least one input stage with internal ground line comprising a relatively quiet ground (QG) and at least one output stage with an output ground line comprising an output ground (PG) said internal and output ground lines being relatively isolated, said output stage comprising an output for delivering data signals of high and low potential, said ground being subject to ground undershoot during transition from high to low potential at the output, said ground undershoot detector circuit comprising: a ground undershoot detector (GUD) transistor element having primary current path first and second nodes defining the transistor element primary current path and a control node for controlling the conducting state of the primary current path, power supply circuit means coupled to said first node, said control node being coupled to quiet ground, and said second node of the primary current path being coupled to output ground for generating at the first node of the primary current path a transient ground undershoot signal (GUS) during transient occurrence of ground undershoot of potential in the output ground relative to the quiet ground causing transient change in the conducting state in the primary current path of the GUD transistor element.

Claim 87

A ground undershoot detector (GUD) circuit for a multistage circuit having at least one input stage with internal ground line comprising a relatively quiet ground (QG) and at least one output stage with an output ground line comprising an output ground (PG) said internal and output ground lines being relatively isolated, said output stage comprising an output for delivering data signals of high and low potential, said ground being subject to ground undershoot during transition from high to low potential at the output, said ground undershoot detector circuit comprising: a ground undershoot detector (GUD) transistor element having primary current path first and second nodes defining the transistor element primary current path and a control node for controlling the conducting state of the primary current path, power supply circuit means coupled to said first node, said control node being coupled to quiet ground, and said second node of the primary current path being coupled to output ground for generating at the first node of the primary current path a transient ground undershoot signal (GUS) during transient occurrence of ground undershoot of potential in the output ground relative to the quiet ground causing transient change in the conducting state in the primary current path of the GUD transistor element.

Claim 88

The ground undershoot detector circuit of claim 74 further comprising a current amplification stage coupled to receive the GUS.

Claim 89

The ground undershoot circuit of claim 75 wherein the stage of current amplification comprises an inverting stage and wherein the GUD circuit delivers a final transient GUS of high potential during transient occurrence of ground undershoot of potential in the output ground.

Claim 90

A supply noise detector circuit for a multi-stage circuit having at least one input stage with internal V cc supply lead comprising a relatively quiet supply (QV) and at least one output stage with an output V cc supply lead comprising an output supply (PV) said internal and output supply leads being relatively isolated, said output stage comprising an output for delivering data signals of high and low potential, said output supply PV being subject to supply noise including V cc droop and overshoot during transition rom low to high potential at the output, said power noise detector circuit comprising: a supply noise detector transistor element having primary current path first and second nodes defining the transistor element primary current path, and a control node for controlling the conducting state of the primary current path, ground circuit means coupled to said second node, said control node being coupled to one of the quiet supply QV and output supply PV, and said first node of the primary current path being coupled to the other of the quiet supply QV and output supply PV for generating at the second node of the primary current path a transient supply noise signal (VNS) during transient occurrence of supply potential differential between the quiet supply QV and output supply PV causing transient change in he conducting state of the primary current path of the supply noise detector transistor element.

Claim 91

A supply noise detector circuit for a multi-stage circuit having at least one input stage with internal V cc supply lead comprising a relatively quiet supply (QV) and at least one output stage with an output V cc supply lead comprising an output supply (PV) said internal and output supply leads being relatively isolated, said output stage comprising an output for delivering data signals of high and low potential, said output supply PV being subject to supply noise including V cc droop and overshoot during transition rom low to high potential at the output, said power noise detector circuit comprising: a supply noise detector transistor element having primary current path first and second nodes defining the transistor element primary current path, and a control node for controlling the conducting state of the primary current path, ground circuit means coupled to said second node, said control node being coupled to one of the quiet supply QV and output supply PV, and said first node of the primary current path being coupled to the other of the quiet supply QV and output supply PV for generating at the second node of the primary current path a transient supply noise signal (VNS) during transient occurrence of supply potential differential between the quiet supply QV and output supply PV causing transient change in he conducting state of the primary current path of the supply noise detector transistor element.

Claim 92

The supply noise detector circuit of claim 77 wherein the supply noise detector transistor element comprises a V cc droop detector (VDD) transistor element, wherein said control node is coupled to the output supply PV, and the first node of the primary current path is coupled to the quiet supply QV for generating at the second node of the primary current path a transient V cc droop signal (VDS) during transient occurrence of V cc droop in potential in the output supply PV relative to the quiet supply QV causing transient change in the conducting state of the primary current path of the VDD transistor element.

Claim 93

The power noise detector circuit of claim 78 wherein the VDD transistor element is an MOS transistor element.

Claim 94

The power noise detector circuit of claim 78 wherein the VDD transistor element is a bipolar transistor element.

Claim 95

The power noise detector circuit of claim 79 wherein the VDD MOS transistor element is a PMOS transistor element, and wherein the first node is the source node, the second node the drain node, and control node the gate node.

Claim 96

The power noise detector circuit of claim 80 wherein the VDD bipolar transistor element is a PNP transistor element, and wherein the first node is the emitter node, the second node is the collector node, and control node the base node.

Claim 97

The power noise detector circuit of claim 78 further comprising a noninverting stage of current amplification coupled to receive the transient VDS and wherein the power noise detector circuit delivers a final transient VDS of high potential during transient occurrence of V cc droop in potential in the output supply PV.

Claim 98

The power noise detector circuit of claim 78 further comprising an inverting stage of current amplification coupled to receive the transient VDS and wherein the power noise detector circuit delivers a final transient VDS output of low potential during transient occurrence of V cc droop in potential in the output supply PV.

Claim 99

The power noise circuit of claim 77 wherein the power noise detector transistor element comprises a V cc overshoot detector (VOD) transistor element, wherein said control node is coupled to quiet supply QV, and said first node of the primary current path is coupled to output supply PV for generating at the second node of the primary current path a transient PV overshoot signal (VOS) output during transient occurrence of PV overshoot of potential in the output supply PV relative to the quiet supply QV causing transient change in the conducting state of the primary current path of the VOD transistor element.

Claim 100

The power noise detector circuit of claim 85 wherein the VOD transistor element is a PMOS transistor element and wherein the first node is the source node, second node the drain node, and control node the gate node.

Claim 101

The power noise detector circuit of claim 85 wherein the VOD transistor element is a bipolar PNP transistor element, wherein the first node is the emitter node, the second node is the collector node, and control node the base node.

Claim 102

The power noise detector circuit of claim 85 further comprising at least one stage of current amplification coupled to receive the transient VOS and wherein the power noise detector circuit delivers a final transient VOS of high potential during transient occurrence of PV overshoot of potential in the output supply PV.