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US5049516A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing semiconductor memory device

Assignee: Mitsubishi Electric Corp
•
Filing: 1989-12-15
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Granted: 1991-09-17
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Expires: 2009-12-15
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Abstract

Abstract An EEPROM formed of three-layer polysilicon is provided. A floating gate is at a second level and a portion thereof is at a first level. A first control gate and a select gate are formed spaced against from each other at the first level and a portion of the second floating gate extends between them for formation of a tunnel region. A second control gate which is kept at the same potential as the first control gate exist at a third level. In this EEPROM, electrons are drawn from the floating gate by applying a high voltage to the select gate.

Inventors

  • 👤 Hideaki Arima

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 17:25
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0433

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 238 words
A method of manufacturing a semiconductor memory device comprising the steps of: preparing a semiconductor substrate of a first conductivity type having a main surface and an impurity concentration; forming a first conductor layer and a second conductor layer spaced apart from each other on said semiconductor substrate through a first insulating film; forming a first impurity layer of a second conductivity type between said first conductor layer and said second conductor layer on the main surface of said semiconductor substrate; forming a third conductor layer on at least said first impurity layer of the second conductivity type, through a second insulating film, and further forming said third conductor layer on said second conductor layer and a region of the main surface of said semiconductor substrate where said first impurity layer of the second conductivity type and said first and second conductor layers are not formed, through a third insulating film; forming a second impurity layer of the second conductivity type on a region of the main surface of said semiconductor substrate where said first through third conductor layers are not formed; forming a third impurity layer of the second conductivity type of a region of the main surface of said semiconductor substrate where said second impurity layer of the second conductivity type and said first through third conductor layers are not formed; and forming a fourth conductor layer on said third conductor layer through an insulating film.
Claim 2
Independent Claim 238 words
A method of manufacturing a semiconductor memory device comprising the steps of: preparing a semiconductor substrate of a first conductivity type having a main surface and an impurity concentration; forming a first conductor layer and a second conductor layer spaced apart from each other on said semiconductor substrate through a first insulating film; forming a first impurity layer of a second conductivity type between said first conductor layer and said second conductor layer on the main surface of said semiconductor substrate; forming a third conductor layer on at least said first impurity layer of the second conductivity type, through a second insulating film, and further forming said third conductor layer on said second conductor layer and a region of the main surface of said semiconductor substrate where said first impurity layer of the second conductivity type and said first and second conductor layers are not formed, through a third insulating film; forming a second impurity layer of the second conductivity type on a region of the main surface of said semiconductor substrate where said first through third conductor layers are not formed; forming a third impurity layer of the second conductivity type of a region of the main surface of said semiconductor substrate where said second impurity layer of the second conductivity type and said first through third conductor layers are not formed; and forming a fourth conductor layer on said third conductor layer through an insulating film.
Claim 3
Dependent Claim 52 words
A method of manufacturing a semiconductor memory device in accordance with claim 1, wherein said step of forming said first conductor layer and said second conductor layer comprises the steps of forming a first polysilicon layer on said first insulating film; and removing a portion of said first polysilicon layer by etching.
Claim 4
Dependent Claim 100 words
A method of manufacturing a semiconductor memory device in accordance with claim 1 wherein, said step of forming said third conductor layer comprises the steps of removing said first insulating film lying on said semiconductor substrate between said first conductor layer and said second conductor layer; forming a second insulating film thinner than said first insulating film on a portion of said semiconductor substrate from which said first insulating film is removed; forming a third insulating film on said first and second conductor layers; and forming a second polysilicon layer on said second insulating film and said third insulating film.
Claim 5
Dependent Claim 39 words
A method of manufacturing a semiconductor device in accordance with claim 1, further comprising the step of forming a wiring layer connected to said second impurity region of the second conductivity type for transferring an electric charge representing information.
Claim 6
Dependent Claim 81 words
A method of manufacturing a semiconductor memory device in accordance with claim 1, wherein said step of forming the first impurity layer of the second conductivity type comprises the steps of forming a photoresist layer on said first conductor layer, said second conductor layer and on portions of said first insulating film and said semiconductor substrate which are not located between said first conductor layer and said second conductor layer; and implanting ions into the main surface of said semiconductor substrate.
Claim 7
Dependent Claim 20 words
A method of manufacturing a semiconductor memory device in accordance with claim 5 wherein the implanted ions are arsenic ions.
Claim 8
Independent Claim 168 words
A method of manufacturing a semiconductor memory device comprising the steps of: preparing a semiconductor substrate of the first conductivity type having a main surface and an impurity concentration; forming a first conductor layer and a second conductor layer spaced apart from each other on said semiconductor substrate and a first insulating film; forming a first impurity layer of a second conductivity type between said first conductor layer and said second conductor layer on the main surface of said semiconductor substrate; forming a third conductor layer to extend on said first impurity layer, said second conductor layer and a region of the main surface of said semiconductor substrate and on an additional insulating film; forming second and third impurity layers of the second conductivity type on regions of the main surface of said semiconductor substrate which are located laterally beyond the extent of said third conductor layer at first and second sides thereof; and forming a fourth conductor layer on said third conductor layer through an insulating film.
Claim 9
Independent Claim 168 words
A method of manufacturing a semiconductor memory device comprising the steps of: preparing a semiconductor substrate of the first conductivity type having a main surface and an impurity concentration; forming a first conductor layer and a second conductor layer spaced apart from each other on said semiconductor substrate and a first insulating film; forming a first impurity layer of a second conductivity type between said first conductor layer and said second conductor layer on the main surface of said semiconductor substrate; forming a third conductor layer to extend on said first impurity layer, said second conductor layer and a region of the main surface of said semiconductor substrate and on an additional insulating film; forming second and third impurity layers of the second conductivity type on regions of the main surface of said semiconductor substrate which are located laterally beyond the extent of said third conductor layer at first and second sides thereof; and forming a fourth conductor layer on said third conductor layer through an insulating film.
Claim 10
Dependent Claim 34 words
A method of manufacturing a semiconductor memory device in accordance with claim 7, wherein said first side of said third conductor layer extends no further than said first conductor layer in said lateral direction.
Claim 11
Dependent Claim 56 words
A method of manufacturing a semiconductor memory device in accordance with claim 7, wherein said step of forming said first conductor layer and said second conductor layer comprises the steps of forming a first polysilicon layer on said substrate and said first insulating film; and removing a predetermined portion of said first polysilicon layer by etching.
Claim 12
Dependent Claim 100 words
A method of manufacturing a semiconductor memory device in accordance with claim 7, wherein said step of forming said third conductor layer comprises the steps of removing said first insulating film lying on said semiconductor substrate between said first conductor layer and said second conductor layer; forming a second insulating film thinner than said first insulating film on a portion of said semiconductor substrate from which said first insulating film is removed; forming a third insulating film on said first and second conductor layers; and forming a second polysilicon layer on said second insulating film and said third insulating film.
Claim 13
Dependent Claim 81 words
A method of manufacturing a semiconductor memory device in accordance with claim 7, wherein said step of forming said first impurity layer of the second conductivity type comprises the steps of forming a photoresist layer on said first conductor layer, said second conductor layer and on portions of said first insulating film and said semiconductor substrate which are not located between said first conductor layer and said second conductor layer; and implanting ions into the main surface of said semiconductor substrate.
Claim 14
Dependent Claim 20 words
A method of manufacturing a semiconductor memory device in accordance with claim 11, wherein the implanted ions are arsenic ions.

References Cited (Backward Citations)

US4307411A Cited
US4355375A Cited
US4425631A Cited
JPS5791561A Cited
US4417264A Cited
JPS58209165A Cited
US4513397A Cited
US4618876A Cited
JPS6345863A Cited
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JPH0243862A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-09-16 1995-03-18 1995-09-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-09-16 1999-03-18 1999-09-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-09-16 2003-03-18 2003-09-17 $7700.00 Window Closed / Lapsed

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