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Method of making a MOS device having a polycide gate

Assignee: Toshiba Corp
•
Filing: 1990-01-18
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Granted: 1991-09-17
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Expires: 2010-01-18
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Abstract

Abstract In a method of manufacturing a semiconductor device of polycide gate structure, a polysilicon layer is formed on the gate insulation film. The polysilicon layer and the gate insulation film are selectively removed to form an opening which reaches the semiconductor substrate in the polysilicon layer and the gate insulation film. After this, a silicide film is formed directly on the polysilicon layer and an exposed part of the semiconductor substrate and then ion-implantation is effected to form source and drain regions. According to the manufacturing method, since the silicide film is formed in direct contact with the semiconductor substrate, charges caused by the ion-implantation can be easily discharged into the semiconductor substrate. Therefore, no gate charge will occur. Further, the gate oxide film is prevented from being brought into contact with the masking photoresist layer by the presence of the polysilicon layer. Therefore, damage of the surface of the gate oxide film due to the direct contact with the photoresist layer will not occur and unwanted material may be prevented from being injected from the photoresist layer into the gate oxide film.

Inventors

  • 👤 Seiichi Mori

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 18:36
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/663; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10P; H10P30/00; H10P30/20; Y; Y10; Y10S; Y10S148/00; Y10S148/019; Y10S148/147; Y10S438/00; Y10S438/91

Claims Analysis

Total Claims: 21
Claim 1
Independent Claim 142 words
A method for manufacturing a semiconductor device having a polycide gate structure, comprising the steps of: forming a gate insulation film on a semiconductor substrate; forming a polysilicon layer on said gate insulation film; selectively removing that portion of said polysilicon layer and that portion of said gate insulation film, which are within a contact region separated from a transistor region, to form an opening which reaches said semiconductor substrate to expose a portion of said semiconductor substrate which is within said contact region; forming a silicide layer in direct contact with said polysilicon layer and said portion of said semiconductor substrate which is exposed by said opening and within said contact region; patterning said polysilicon layer and said silicide layer to form a polycide gate electrode; and after forming the silicide layer, effecting an ion-implantation to form source and drain regions.
Claim 2
Independent Claim 142 words
A method for manufacturing a semiconductor device having a polycide gate structure, comprising the steps of: forming a gate insulation film on a semiconductor substrate; forming a polysilicon layer on said gate insulation film; selectively removing that portion of said polysilicon layer and that portion of said gate insulation film, which are within a contact region separated from a transistor region, to form an opening which reaches said semiconductor substrate to expose a portion of said semiconductor substrate which is within said contact region; forming a silicide layer in direct contact with said polysilicon layer and said portion of said semiconductor substrate which is exposed by said opening and within said contact region; patterning said polysilicon layer and said silicide layer to form a polycide gate electrode; and after forming the silicide layer, effecting an ion-implantation to form source and drain regions.
Claim 3
Dependent Claim 19 words
A manufacturing method according to claim 1, wherein the step of forming said silicide layer includes a CVD process.
Claim 4
Dependent Claim 19 words
A manufacturing method according to claim 1, wherein the step of forming said silicide layer includes a sputtering process.
Claim 5
Dependent Claim 15 words
A manufacturing method according to claim 1, wherein said silicide layer is a WSi layer.
Claim 6
Dependent Claim 15 words
A manufacturing method according to claim 1, wherein said silicide layer is a MoSi layer.
Claim 7
Dependent Claim 15 words
A manufacturing method according to claim 1, wherein said silicide layer is a TiSi layer.
Claim 8
Independent Claim 115 words
A method for manufacturing a semiconductor device having a polycide gate structure, comprising the steps of: forming a gate insulation film on a semiconductor substrate; forming a polysilicon layer on said gate insulation film; selectively removing said polysilicon layer and said gate insulation film to form an opening which reaches said semiconductor substrate; forming a silicide layer in direct contact with said polysilicon layer and a portion of said semiconductor substrate which is exposed by said opening; after forming the silicide layer, effecting an ion-implantation to form source and drain regions; and selectively removing said silicide layer and said polysilicon layer to separate an area acting as a polycide age electrode from said semiconductor substrate.
Claim 9
Independent Claim 115 words
A method for manufacturing a semiconductor device having a polycide gate structure, comprising the steps of: forming a gate insulation film on a semiconductor substrate; forming a polysilicon layer on said gate insulation film; selectively removing said polysilicon layer and said gate insulation film to form an opening which reaches said semiconductor substrate; forming a silicide layer in direct contact with said polysilicon layer and a portion of said semiconductor substrate which is exposed by said opening; after forming the silicide layer, effecting an ion-implantation to form source and drain regions; and selectively removing said silicide layer and said polysilicon layer to separate an area acting as a polycide age electrode from said semiconductor substrate.
Claim 10
Dependent Claim 19 words
A manufacturing method according to claim 7, wherein the step of forming said silicide layer includes a CVD process.
Claim 11
Dependent Claim 19 words
A manufacturing method according to claim 7, wherein the step of forming said silicide layer includes a sputtering process.
Claim 12
Dependent Claim 15 words
A manufacturing method according to claim 7, wherein said silicide layer is a WSi layer.
Claim 13
Dependent Claim 15 words
A manufacturing method according to claim 7, wherein said silicide layer is a MoSi layer.
Claim 14
Dependent Claim 15 words
A manufacturing method according to claim 7, wherein said silicide layer is a TiSi layer.
Claim 15
Independent Claim 165 words
A method for manufacturing a semiconductor device having a polycide gate structure, comprising the steps of: forming a gate insulation film on a semiconductor substrate; forming a polysilicon layer on said gate insulation film; selectively removing that portion of said polysilicon layer and that portion of said gate insulation film, which are within a contact region separated from a transistor region, to form an opening which reaches said semiconductor substrate to expose a portion of said semiconductor substrate which is within said contact region; forming a silicide layer in direct contact with said polysilicon layer and said portion of said semiconductor substrate which is exposed by said opening and within said contact region; patterning said polysilicon layer and said silicide layer to form a polycide gate electrode; after forming the silicide layer, effecting an ion-implantation to form source and drain regions; and selectively removing said silicide layer and said polysilicon layer to separate an area acting as a polycide gate electrode from said semiconductor substrate.
Claim 16
Independent Claim 165 words
A method for manufacturing a semiconductor device having a polycide gate structure, comprising the steps of: forming a gate insulation film on a semiconductor substrate; forming a polysilicon layer on said gate insulation film; selectively removing that portion of said polysilicon layer and that portion of said gate insulation film, which are within a contact region separated from a transistor region, to form an opening which reaches said semiconductor substrate to expose a portion of said semiconductor substrate which is within said contact region; forming a silicide layer in direct contact with said polysilicon layer and said portion of said semiconductor substrate which is exposed by said opening and within said contact region; patterning said polysilicon layer and said silicide layer to form a polycide gate electrode; after forming the silicide layer, effecting an ion-implantation to form source and drain regions; and selectively removing said silicide layer and said polysilicon layer to separate an area acting as a polycide gate electrode from said semiconductor substrate.
Claim 17
Dependent Claim 19 words
A manufacturing method according to claim 13, wherein the step of forming said silicide layer includes a CVD process.
Claim 18
Dependent Claim 19 words
A manufacturing method according to claim 13, wherein the step of forming said silicide layer includes a sputtering process.
Claim 19
Dependent Claim 15 words
A manufacturing method according to claim 13, wherein said silicide layer is a WSi layer.
Claim 20
Dependent Claim 15 words
A manufacturing method according to claim 13, wherein said silicide layer is a MoSi layer.
Claim 21
Dependent Claim 15 words
A manufacturing method according to claim 13, wherein said silicide layer is a TiSi layer.

References Cited (Backward Citations)

FR2406302A1 Cited
JPS57100768A Cited
US4551908A Cited
US4558507A Cited
US4740479A Cited
WO1987000967A1 Cited
US4788160A Cited
US4859278A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-09-16 1995-03-18 1995-09-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-09-16 1999-03-18 1999-09-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-09-16 2003-03-18 2003-09-17 $7700.00 Window Closed / Lapsed

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