Patent US5047357A successfully refreshed from Google Patents.
US5047357A
Expired / Lapsed
US
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Method for forming emitters in a BiCMOS process
Assignee: Texas Instruments Inc
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Filing: 1989-02-03
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Granted: 1991-09-10
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Expires: 2009-02-03
Abstract
Abstract A bipolar transistor and method of making the same is disclosed. The transistor has an emitter region which is diffused from polysilicon into the intrinsic base region, where the polysilicon is doped with two dopant species of different diffusivity. The impurity concentration of the higher diffusivity species, for example phosphorous, can be selected to define the emitter junction depth, which is preferably shallow, while the impurity concentration of the lower diffusivity species, for example arsenic, can be selected to provide a high conductivity emitter electrode, as well as reduce the sensitivity of the emitter electrode to counterdoping from the implantation of the extrinsic base region. The structure is compatible with BiCMOS processing, as the same anneal can be used to diffuse the emitter and the source/drains of the MOS transistors, with the emitter junction depth optimized via the implant conditions of the higher diffusivity species. The emitter electrode according to the invention can also be exposed to the opposite conductivity type source/drain implant, with reduced sensitivity to counterdoping.
Inventors
- 👤 Robert H. Eklund
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:53
CPC Classifications
H; H10; H10P; H10P32/00; H10P32/10; H10P32/17; H10P32/171; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10P14/00; H10P14/60; H10P14/61; H10P32/14; H10P32/1408; H10P32/1414; Y; Y10; Y10S; Y10S148/00; Y10S148/123; Y10S148/124; Y10S148/151
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
128 words
A method for fabricating a bipolar transistor at a surface of a semiconductor body, comprising: forming a collector region of a first conductivity type in said body; forming a base region disposed within said collector region and at said surface, said base region of a second conductivity type; forming a semiconductor layer in contact with said base region at said surface, said semiconductor layer doped with first and second dopants of said first conductivity type, said first dopant having a relatively high diffusivity relative to said second dopant; heating said semiconductor body so as to diffuse said first dopant from said semiconductor layer into said base region to form an emitter region while substantially retaining said second dopant in said emitter electrode to provide low emitter electrode resistance.
Claim 2
Independent Claim
128 words
A method for fabricating a bipolar transistor at a surface of a semiconductor body, comprising: forming a collector region of a first conductivity type in said body; forming a base region disposed within said collector region and at said surface, said base region of a second conductivity type; forming a semiconductor layer in contact with said base region at said surface, said semiconductor layer doped with first and second dopants of said first conductivity type, said first dopant having a relatively high diffusivity relative to said second dopant; heating said semiconductor body so as to diffuse said first dopant from said semiconductor layer into said base region to form an emitter region while substantially retaining said second dopant in said emitter electrode to provide low emitter electrode resistance.
Claim 3
Dependent Claim
57 words
The method of claim 1, further comprising: forming a dielectric layer over said base region prior to said step of forming a semiconductor layer; and etching a contact through said dielectric layer to define an emitter contact, prior to said step of forming a semiconductor layer; wherein said semiconductor layer contacts said base region through said contact.
Claim 4
Dependent Claim
19 words
The method of claim 1, wherein said first conductivity type is n-type, and said second conductivity type is p-type.
Claim 5
Dependent Claim
11 words
The method of claim 3, wherein said first dopant is phosphorous.
Claim 6
Dependent Claim
11 words
The method of claim 4, wherein said second dopant is arsenic.
Claim 7
Dependent Claim
12 words
The method of claim 1, wherein said semiconductor layer is polycrystalline silicon.
Claim 8
Dependent Claim
44 words
The method of claim 1, further comprising: etching said semiconductor layer to define an emitter electrode, prior to said heating step; doping a portion of said base region with dopant of said second conductivity type, wherein said emitter electrode is exposed to said doping.
Claim 9
Dependent Claim
13 words
The method of claim 7, wherein said doping is performed by ion implantation.
Claim 10
Dependent Claim
18 words
The method of claim 1, further comprising: ion implanting said first and second dopants into said semiconductor layer.
Claim 11
Independent Claim
184 words
A method for forming bipolar and field effect transistors at a surface of a semiconductor body, comprising: forming a collector region of a first conductivity type in said body; forming a base region disposed within said collector region at a first location of said surface, said base region of a second conductivity type; forming a first well of said first conductivity type at a second location of said surface; forming a gate dielectric over said first well; forming a semiconductor layer in contact with said base region and overlying said gate dielectric, said semiconductor layer doped with first and second dopants of said first conductivity type, said first dopant having a relatively high diffusivity relative to said second dopant; removing selected portions of said semiconductor layer to define an emitter electrode in contact with said base region and a gate electrode overlying said well; doping portions of said first well near said gate electrode with dopant of said second conductivity type; and heating said semiconductor body to diffuse said first dopant from said semiconductor layer into said base region to form an emitter region.
Claim 12
Independent Claim
184 words
A method for forming bipolar and field effect transistors at a surface of a semiconductor body, comprising: forming a collector region of a first conductivity type in said body; forming a base region disposed within said collector region at a first location of said surface, said base region of a second conductivity type; forming a first well of said first conductivity type at a second location of said surface; forming a gate dielectric over said first well; forming a semiconductor layer in contact with said base region and overlying said gate dielectric, said semiconductor layer doped with first and second dopants of said first conductivity type, said first dopant having a relatively high diffusivity relative to said second dopant; removing selected portions of said semiconductor layer to define an emitter electrode in contact with said base region and a gate electrode overlying said well; doping portions of said first well near said gate electrode with dopant of said second conductivity type; and heating said semiconductor body to diffuse said first dopant from said semiconductor layer into said base region to form an emitter region.
Claim 13
Dependent Claim
36 words
The method of claim 10, wherein said step of doping portions of said first well comprises ion implanting; and wherein said emitter electrode is exposed to said ion implanting of dopant of said second conductivity type.
Claim 14
Dependent Claim
19 words
The method of claim 10, wherein said first conductivity type is n-type, and said second conductivity type is p-type.
Claim 15
Dependent Claim
11 words
The method of claim 12, wherein said first dopant is phosphorous.
Claim 16
Dependent Claim
11 words
The method of claim 13, wherein said second dopant is arsenic.
Claim 17
Dependent Claim
12 words
The method of claim 10, wherein said semiconductor layer is polycrystalline silicon.
Claim 18
Dependent Claim
102 words
The method of claim 10, further comprising: forming a second well of said second conductivity type at a third location of said surface; wherein said step of forming a gate dielectric also forms a gate dielectric over said second well; wherein said step of removing selected portions of said semiconductor layer also defines a gate electrode over said second well; and further comprising: implanting dopant of said first conductivity type into portions of said second well near said gate electrode; wherein said step of heating said semiconductor body also diffuses said implant dopant of said first conductivity type into said second well.
Claim 19
Dependent Claim
24 words
The method of claim 10, further comprising: making electrical connections from the eternal terminals of a package and said bipolar and field effect transistors.
Claim 20
Independent Claim
131 words
A method for fabricating a bipolar transistor at a surface of a semiconductor body, comprising: forming a collector region of a first conductivity type in said body; forming a base region disposed within said collector region and at said surface, said base region of a second conductivity type; forming a semiconductor emitter electrode in contact with said base region at said surface, said semiconductor emitter electrode doped with first and second dopants of said first conductivity type, said first dopant having a relatively high diffusivity relative to said second dopant; heating said semiconductor body so as to diffuse said first dopant from said semiconductor emitter electrode into said base region to form an emitter region while substantially retaining said second dopant in said emitter electrode to provide low emitter electrode resistance.
Claim 21
Independent Claim
131 words
A method for fabricating a bipolar transistor at a surface of a semiconductor body, comprising: forming a collector region of a first conductivity type in said body; forming a base region disposed within said collector region and at said surface, said base region of a second conductivity type; forming a semiconductor emitter electrode in contact with said base region at said surface, said semiconductor emitter electrode doped with first and second dopants of said first conductivity type, said first dopant having a relatively high diffusivity relative to said second dopant; heating said semiconductor body so as to diffuse said first dopant from said semiconductor emitter electrode into said base region to form an emitter region while substantially retaining said second dopant in said emitter electrode to provide low emitter electrode resistance.
Claim 22
Dependent Claim
60 words
The method of claim 18, further comprising: forming a dielectric layer over said base region prior to said step of forming a semiconductor emitter electrode; and etching a via through said dielectric layer to define a contact area prior to said step of forming a semiconductor emitter electrode; wherein said semiconductor emitter electrode contacts said base region through said via.
Claim 23
Dependent Claim
11 words
The method of claim 18, wherein said first dopant is phosphorous.
Claim 24
Dependent Claim
11 words
The method of claim 28, wherein said second dopant is arsenic.
Claim 25
Dependent Claim
12 words
The method of claim 18, wherein said semiconductor layer is polycrystalline silicon.
Claim 26
Dependent Claim
19 words
The method of claim 18, further comprising: ion implanting said first and second dopants into said semiconductor emitter electrodes.
Claim 27
Independent Claim
170 words
A method for forming bipolar and field effect transistors at a surface of a semiconductor body, comprising: forming a collector region of a first conductivity type in said body; forming a base region disposed within said collector region at a first location of said surface, said base region of a second conductivity type; forming a first well of said first conductivity type at a second location of said surface; forming a semiconductor emitter electrode in contact with said base region, said emitter electrode doped with first and second dopants of said first conductivity type, said first dopant having a relatively high diffusivity relative to said second dopant; forming a semiconductor gate electrode overlying said well, said gate electrode doped with at least one of said first and second dopants; doping portions of said first well near said gate electrode with dopant of said second conductivity type; and heating said semiconductor body to diffuse said first dopant from said semiconductor emitter electrode into said base region to form an emitter region.
Claim 28
Independent Claim
170 words
A method for forming bipolar and field effect transistors at a surface of a semiconductor body, comprising: forming a collector region of a first conductivity type in said body; forming a base region disposed within said collector region at a first location of said surface, said base region of a second conductivity type; forming a first well of said first conductivity type at a second location of said surface; forming a semiconductor emitter electrode in contact with said base region, said emitter electrode doped with first and second dopants of said first conductivity type, said first dopant having a relatively high diffusivity relative to said second dopant; forming a semiconductor gate electrode overlying said well, said gate electrode doped with at least one of said first and second dopants; doping portions of said first well near said gate electrode with dopant of said second conductivity type; and heating said semiconductor body to diffuse said first dopant from said semiconductor emitter electrode into said base region to form an emitter region.
Claim 29
Dependent Claim
21 words
The method of claim 24, wherein said first conductivity type is n type, and said second conductivity type is p type.
Claim 30
Dependent Claim
11 words
The method of claim 24, wherein said first dopant is phosphorous.
Claim 31
Dependent Claim
11 words
The method of claim 26, wherein said second dopant is arsenic.
Claim 32
Dependent Claim
13 words
The method of claim 24, wherein said semiconductor emitter electrode is polycrystalline silicon.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-09 | 1995-03-11 | 1995-09-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-09 | 1999-03-11 | 1999-09-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-09 | 2003-03-11 | 2003-09-10 | $7700.00 | Window Closed / Lapsed |