Patent US5045720A successfully refreshed from Google Patents.
US5045720A
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US
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Method for selecting a spare column and a circuit thereof
Assignee: Samsung Electronics Co Ltd
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Filing: 1990-09-05
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Granted: 1991-09-03
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Expires: 2010-09-05
Abstract
Abstract There is provided a spare column selection circuit comprising a line switching pair arranged between a spare input/output line pair connected to a spare bit line and a normal input/output line pair connected to a normal bit line pair. The line switching pair are driven by an output of a spare column decoder. A normal line pull-up pair are connected to the corresponding normal input/output line so as to be driven by the output of the spare column decoder. An inverter produces a clock signal having an inverted signal phase against a clock from a spare column decoder, and the inverted clock signal connects the spare input/output line pair to the spare bit line pair.
Inventors
- 👤 Myung-Ho Bae
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:56
CPC Classifications
G; G11; G11C; G11C8/00; G11C29/00; G11C29/70; G11C29/78; G11C29/84; G11C29/846
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
84 words
A method for selecting a spare column of a memory device in which a spare input/output line unit pair is connected to a spare bit line pair and a normal input/output line pair is connected to a normal bit line pair, the method comprising electrically separating the spare input/output line unit pair and the normal input/output line pair from each other when the spare column is selected, and connecting the spare and normal input/output pairs to each other when the normal column is selected.
Claim 2
Independent Claim
84 words
A method for selecting a spare column of a memory device in which a spare input/output line unit pair is connected to a spare bit line pair and a normal input/output line pair is connected to a normal bit line pair, the method comprising electrically separating the spare input/output line unit pair and the normal input/output line pair from each other when the spare column is selected, and connecting the spare and normal input/output pairs to each other when the normal column is selected.
Claim 3
Dependent Claim
56 words
A method for selecting a spare column as claimed in claim 1 including applying a pull-up supply voltage to the normal input/output line pair connected to the normal bit line pair so as to prepare a next read/write cycle at a time when the spare bit line pair and the normal bit line pair are separated.
Claim 4
Dependent Claim
90 words
A spare column selection circuit comprising: a line switching pair connected between: a spare input/output line pair each of which is connected to spare bit lines, and a normal input/output line pair each of which is connected to normal bit lines, the line switching pair being driven by an output of a spare column decoder; and a normal line pull-up pair each connected to the corresponding normal input/output lines and driven by the output of the spare column decoder for charging the normal input/output line pair to a pull-up voltage.
Claim 5
Dependent Claim
90 words
A spare column selection circuit comprising: a line switching pair connected between: a spare input/output line pair each of which is connected to spare bit lines, and a normal input/output line pair each of which is connected to normal bit lines, the line switching pair being driven by an output of a spare column decoder; and a normal line pull-up pair each connected to the corresponding normal input/output lines and driven by the output of the spare column decoder for charging the normal input/output line pair to a pull-up voltage.
Claim 6
Dependent Claim
36 words
A spare column selection circuit as in claim 4 further comprising circuit means for connecting the spare input/output line pair to the spare bit line pair subsequent to the charging of the normal line pull-up pair.
Claim 7
Independent Claim
183 words
A method for operating a semiconductor integrated circuit memory over a plurality of memory cycles, the memory including a normal memory cell array connected to normal bit lines, a spare memory cell array connected to spare bit lines, means for connecting and disconnecting the spare bit lines to and from spare input/output lines, a normal column decoder for selecting the normal bit lines, and a spare column decoder for selecting the spare bit lines, said method comprising determining, during each cycle of operation of the memory, the fault condition of the normal portions of the memory, and, in the absence of a fault conduction, operating the memory in a normal column mode in which the normal bit lines are connected to the spare input/output lines while the spare bit lines are maintained disconnected from the spare input/output lines, and, in response to the presence of a fault condition, operating the memory in a spare column mode in which the spare bit lines are connected to the spare input/output lines subsequent to the disconnecting of the normal bit lines from the spare input/output lines.
Claim 8
Independent Claim
183 words
A method for operating a semiconductor integrated circuit memory over a plurality of memory cycles, the memory including a normal memory cell array connected to normal bit lines, a spare memory cell array connected to spare bit lines, means for connecting and disconnecting the spare bit lines to and from spare input/output lines, a normal column decoder for selecting the normal bit lines, and a spare column decoder for selecting the spare bit lines, said method comprising determining, during each cycle of operation of the memory, the fault condition of the normal portions of the memory, and, in the absence of a fault conduction, operating the memory in a normal column mode in which the normal bit lines are connected to the spare input/output lines while the spare bit lines are maintained disconnected from the spare input/output lines, and, in response to the presence of a fault condition, operating the memory in a spare column mode in which the spare bit lines are connected to the spare input/output lines subsequent to the disconnecting of the normal bit lines from the spare input/output lines.
Claim 9
Dependent Claim
39 words
A method according to claim 5 wherein, in the spare column mode of operation, the normal bit lines are charged to a pull-up supply voltage prior to the connecting of the spare bit lines to the spare input/output lines.
Claim 10
Dependent Claim
149 words
In a semiconductor integrated circuit memory comprising a normal memory cell array connected to normal bit lines, a spare memory cell array connected to spare bit lines, a normal column decoder for selecting the normal bit lines, a spare column decoder for selecting the spare bit lines, first means for connecting or disconnecting the normal bit lines to and from normal input/output lines, and second means for connecting or disconnecting the spare bit lines to spare input/output lines, the improvement comprising a line switching means responsive to output signals from the spare column decoder for, during each cycle of operation of the memory, either connecting the normal bit lines to the spare input/output lines while the spare bit lines are disconnected from the spare input/output lines, or connecting the spare bit lines to the spare input/output lines while the normal bit lines are disconnected from the spare input/output lines.
Claim 11
Dependent Claim
149 words
In a semiconductor integrated circuit memory comprising a normal memory cell array connected to normal bit lines, a spare memory cell array connected to spare bit lines, a normal column decoder for selecting the normal bit lines, a spare column decoder for selecting the spare bit lines, first means for connecting or disconnecting the normal bit lines to and from normal input/output lines, and second means for connecting or disconnecting the spare bit lines to spare input/output lines, the improvement comprising a line switching means responsive to output signals from the spare column decoder for, during each cycle of operation of the memory, either connecting the normal bit lines to the spare input/output lines while the spare bit lines are disconnected from the spare input/output lines, or connecting the spare bit lines to the spare input/output lines while the normal bit lines are disconnected from the spare input/output lines.
Claim 12
Dependent Claim
49 words
A memory according to claim 7 including circuit means, responsive to output signals from the spare column decoder during each cycle of operation of the memory, for charging the normal bit lines to a pull-up supply voltage prior to connecting the spare bit lines to the spare input/output lines.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-02 | 1995-03-04 | 1995-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-02 | 1999-03-04 | 1999-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-02 | 2003-03-04 | 2003-09-03 | $7700.00 | Window Closed / Lapsed |