Redundancy system with distributed mapping

Claim 2

A distributed mapping system for interconnecting multiple subsystems, some of which are redundant or defective, comprising: address bus means for selecting a particular subsystem for use in an operation or for performance of some function; and mapping circuitry associated with each of the subsystems, and having first storage means, for registering a physical address of the subsystem, second storage means, for registering a logical address for accessing the subsystem, means for modifying the logical address of the subsystem during a configuration mode of operation, means for comparing the logical address of the subsystem with an address impressed on the address bus means during a normal mode of operation, and means for activating the subsystem in response to the detection of a match by the means for comparing; and wherein the means for modifying the logical address of the subsystem includes means for comparing the physical address of the subsystem stored in the first storage means with a physical address impressed on the address bus means during the configuration mode of operation, and generating a match signal if the physical address matches the address on the address bus means, and means responsive to the match signal, for enabling the transfer of a logical address from the address bus means to the second storage means, for later use in the normal mode of operation.

Claim 3

A distributed mapping system as defined in claim 1, wherein: the address bus means has only a single address bus, the use of which is multiplexed to configure the system by associating physical and logical addresses.

Claim 4

A distributed mapping system as defined in claim 1, wherein: the address bus means includes a physical address bus for selecting a particular physical subsystem, and a logical address bus for storing a logical address in the selected physical subsystem, and for selecting subsystems in accordance with their previously stored logical addresses.

Claim 5

A distributed mapping system as defined in claim 1, and further comprising: means for storing a null logical address in the second storage means of selected subsystems, to indicate that the selected subsystems are defective or out of service for some other reason.

Claim 6

A distributed mapping system as defined in claim 1, wherein: the multiple subsystems are formed as part of a common semiconductor wafer.

Claim 7

A distributed mapping system as defined in claim 5, wherein: the semiconductor wafer is of silicon material.

Claim 8

A distributed mapping system as defined in claim 5, wherein: the semiconductor wafer is of gallium arsenide material.

Claim 9

A distributed mapping system as defined in claim 1, wherein: the system is formed as a plurality of individual semiconductor chips, each containing one or more subsystems, and mounted on a semiconductor wafer.

Claim 10

A distributed mapping system for interconnecting multiple subsystems, some of which are redundant or defective, each subsystem having a unique physical address and having circuitry connected to perform some desired function, the system comprising: address bus means for selecting a subsystem for purposes of configuring the mapping system, or for performance of the desired function; mapping circuitry associated with each of the subsystems, and having a first register, for storing the physical address of the subsystem, a second register, for storing a logical address of the subsystem, a first comparator circuit for comparing the physical address of the subsystem with a physical address supplied on the address bus means, a register control circuit activated only in response to a match signal from the first comparator circuit, for generating a register control signal that enables the second register to receive and store a logical address placed on the address bus means immediately after the physical address with which it is to be associated, a second comparator circuit for comparing the logical address stored in the second register with a logical address placed on the address bus means, to permit logical addressing of the subsystems after their logical addresses have been stored in the second registers, and a subsystem control circuit, responsive to a match signal from the second comparator circuit, for activating the corresponding subsystem circuitry.

Claim 11

A distributed mapping system for interconnecting multiple subsystems, some of which are redundant or defective, each subsystem having a unique physical address and having circuitry connected to perform some desired function, the system comprising: address bus means for selecting a subsystem for purposes of configuring the mapping system, or for performance of the desired function; mapping circuitry associated with each of the subsystems, and having a first register, for storing the physical address of the subsystem, a second register, for storing a logical address of the subsystem, a first comparator circuit for comparing the physical address of the subsystem with a physical address supplied on the address bus means, a register control circuit activated only in response to a match signal from the first comparator circuit, for generating a register control signal that enables the second register to receive and store a logical address placed on the address bus means immediately after the physical address with which it is to be associated, a second comparator circuit for comparing the logical address stored in the second register with a logical address placed on the address bus means, to permit logical addressing of the subsystems after their logical addresses have been stored in the second registers, and a subsystem control circuit, responsive to a match signal from the second comparator circuit, for activating the corresponding subsystem circuitry.

Claim 12

A distributed mapping system as defined in claim 9, and further comprising: means for storing a null code in each second register associated with a defective or spare subsystem that is to be excluded from interconnection with other subsystems.

Claim 13

A distributed mapping system as defined in claim 9, wherein: the address bus means has only a single address bus, the use of which is multiplexed to configure the system by associated physical and logical addresses.

Claim 14

A distributed mapping system as defined in claim 9, wherein: the address bus means includes a physical address bus for selecting a particular physical subsystem, and a logical address bus for storing a logical address in the selected physical subsystem, and for selecting subsystems in accordance with their previously stored logical addresses.

Claim 15

A distributed mapping system, comprising: a plurality of subsystems, some of which are redundant or defective; data bus means, interconnecting the subsystems, for communicating information with the subsystems; logical address bus means, interconnecting the subsystems, for providing a logical address bus signal designating a particular subsystem which is to communicate with the data bus; and enable/disable means for for transmitting a disable signal to the subsystems when the logical addresses of one or more of the subsystems is to be reassigned; wherein each subsystem includes a mapping circuit having first register means for storing a logical address for identifying the subsystem, first comparator means for comparing the logical address stored in the first register means of the subsystem with the logical address designated by the logical address bus signal and, if said two logical addresses match, connecting the subsystem to communicate with the data bus in response to a match signal from the first comparator means, and means for modifying the logical address stored in the first register means in response to the disable signal.

Claim 16

A distributed mapping system, comprising: a plurality of subsystems, some of which are redundant or defective; data bus means, interconnecting the subsystems, for communicating information with the subsystems; logical address bus means, interconnecting the subsystems, for providing a logical address bus signal designating a particular subsystem which is to communicate with the data bus; and enable/disable means for for transmitting a disable signal to the subsystems when the logical addresses of one or more of the subsystems is to be reassigned; wherein each subsystem includes a mapping circuit having first register means for storing a logical address for identifying the subsystem, first comparator means for comparing the logical address stored in the first register means of the subsystem with the logical address designated by the logical address bus signal and, if said two logical addresses match, connecting the subsystem to communicate with the data bus in response to a match signal from the first comparator means, and means for modifying the logical address stored in the first register means in response to the disable signal.

Claim 17

A distributed mapping system as defined in claim 13, wherein, in each subsystem, the means for modifying the logical address includes: means, responsive to the disable signal, for storing in the first register means the logical address designated by the logical address bus signal.

Claim 18

A distributed mapping system as defined in claim 13, and further comprising: a physical address bus, interconnecting the subsystems, for providing a physical address bus signal designating a particular subsystem whose logical address is to be reassigned; wherein, in each subsystem, the mapping circuit further includes a second register means for storing a physical address identifying the subsystem; and wherein, in each subsystem, the means for modifying the logical address includes second comparator means, responsive to the disable signal, for comparing the physical address stored in the second register means of the subsystem with the physical address designated by the physical address bus signal and, if said two physical addresses match, storing in the first register means the logical address designated by the logical address bus signal.

Claim 19

A distributed mapping system as defined in claim 13, and further comprising: means for storing a null logical address in the first register means of selected subsystems, to indicate that the selected subsystems are defective or out of service for some other reason.

Claim 20

A distributed mapping system as defined in claim 13, wherein: the multiple subsystems are formed as part of a common semiconductor wafer.

Claim 21

A distributed mapping system as defined in claim 17, wherein: the semiconductor wafer is of silicon material.

Claim 22

A distributed mapping system as defined in claim 17, wherein: the semiconductor wafer is of gallium arsenide material.

Claim 23

A distributed mapping system, as defined in claim 13, wherein: the system is formed as a plurality of individual semiconductor chips, each containing one or more subsystems, and mounted on a semiconductor wafer.