Semiconductor device having compound semiconductor FET of E/D structure with high margin

Claim 2

A semiconductor device comprising: a substrate; a first semiconductor layer with a low impurity density provided on said substrate; an N-type second semiconductor layer with a high impurity density provided on said first semiconductor layer, said second semiconductor layer acting as a channel layer; a third semiconductor layer with a low impurity density provided on said second semiconductor layer, an electron affinity of said third semiconductor layer being smaller than that of said second semiconductor layer, and said third semiconductor layer having a first surface portion and a second surface portion; an N-type fourth semiconductor layer with a high impurity density provided on said second surface portion of said third semiconductor layer; a fifth semiconductor layer with a low impurity density provided on said fourth semiconductor layer, an impurity density of said second semiconductor layer being higher than those of said first, third and fifth semiconductor layers, and an impurity density of said fourth semiconductor layer being higher than those of said first, third and fifth semiconductor layers; a first control electrode provided on said first surface portion of said third semiconductor layer; a first N-type high impurity density region and a second N-type high impurity density region provided respectively on both sides of said first control electrode, said first and second N-type high impurity density regions extending from said first surface portion of said third semiconductor layer and reaching said second semiconductor layer, impurity densities of said first and second N-type high impurity density regions being higher than those of said second and third semiconductor layers; a first electrode and a second electrode respectively provided on said first N-type high impurity density region and on said second N-type high impurity density region; a second control electrode provided on said fifth semiconductor layer; a third N-type high impurity density region and a fourth N-type high impurity density region provided respectively on both sides of said second control electrode, said third and fourth N-type high impurity density regions extending from a surface of said fifth semiconductor layer and reaching said second semiconductor layer, impurity densities of said third and fourth N-type high impurity density regions being higher than those of said second, third, fourth and fifth semiconductor layers; and a third electrode and a fourth electrode respectively provided on said third N-type high impurity density region and on said fourth N-type high impurity density region.

Claim 3

A semiconductor device as recited in claim 1, further comprising means for connecting said second electrode and said third electrode.

Claim 4

A semiconductor device as recited in claim 1, further comprising a first N-type intermediate impurity density region and a second N-type intermediate impurity density region with impurity densities lower than those of said first and second N-type high impurity density regions, said first and second N-type intermediate impurity regions being provided respectively between said first and second N-type high impurity density regions and said first control electrode, said first and second N-type intermediate impurity regions extending from said first surface portion of said third semiconductor layer and reaching said second semiconductor layer, and a third N-type intermediate impurity density region and a fourth N-type intermediate impurity density region with impurity densities lower than those third and fourth N-type high impurity density regions, said third and fourth N-type intermediate impurity regions being provided respectively between said third and fourth N-type high impurity density regions and said second control electrode, said third and fourth N-type intermediate impurity regions extending from said surface of said fifth semiconductor layer and reaching said second semiconductor layer.

Claim 5

A semiconductor device as recited in claim 1, further comprising a sixth semiconductor layer provided between said first semiconductor layer and said substrate, said sixth semiconductor layer having an impurity density lower than that of said second semiconductor layer and having and electron affinity smaller than that of said first semiconductor layer.

Claim 6

A semiconductor device as recited in claim 1, wherein said first semiconductor layer is a high resistance buffer layer, an impurity density of said high resistance buffer layer being less than 1×10 16 cm -3 for an N-type impurity.

Claim 7

A semiconductor device as recited in claim 1, wherein said first semiconductor layer is a high resistance buffer layer, an impurity density of said high resistance buffer layer being less than 5×10 17 cm -3 for a P-type impurity.

Claim 8

A semiconductor device as recited in claim 1, wherein said impurity density of said second semiconductor layer is in the range of 5×10 17 -5×10 18 cm -3 , said impurity density of said third semiconductor layer is in the range of 1×10 13 -1×10 17 cm -3 , and said impurity density of said fourth semiconductor layer is in the range of 1×10 17 -5×10 18 cm -3 .

Claim 9

A semiconductor device as recited in claim 7, wherein a film thickness of said second semiconductor layer is in the range of 50-500 Å, a film thickness of said third semiconductor layer is in the range of 50-1000 Å, and a film thickness of said fourth semiconductor layer is in the range of 50-500 Å.

Claim 10

A semiconductor device as recited in claim 1, wherein said first semiconductor layer is an undoped gallium arsenide layer, said second semiconductor layer is an N-type gallium arsenide layer, said third semiconductor layer is an undoped aluminum gallium arsenide layer, said fourth semiconductor layer is an N-type gallium arsenide layer and said fifth semiconductor layer is an undoped gallium arsenide layer.

Claim 11

A semiconductor device as claimed in claim 9, further comprising an undoped aluminum gallium arsenide layer provided between said first semiconductor layer and said substrate.

Claim 12

A semiconductor device comprising: a substrate; a first semiconductor layer with a low impurity density provided on said substrate; a second semiconductor layer with a low impurity density provided on said first semiconductor substrate, an electron affinity of said first semiconductor layer being smaller than that of said second semiconductor layer; an N-type third semiconductor layer with a high impurity density provided on said second semiconductor layer, said third semiconductor layer acting as a channel layer; a fourth semiconductor layer with a low impurity density provided on said third semiconductor layer, the electron affinity of said fourth semiconductor layer being smaller than that of said third semiconductor layer, and said fourth semiconductor layer having a first surface portion and a second surface portion; a fifth semiconductor layer with a low impurity density provided on said second surface portion of said fourth semiconductor layer, an impurity density of said third semiconductor layer being higher than those of said first, second, fourth and fifth semiconductor layers; a first control electrode provided on said first surface portion of said fourth semiconductor layer; a first N-type high impurity density region and a second N-type high impurity density region provided respectively on both sides of said first control electrode, said first and second N-type high impurity density regions extending from said first surface portion of said fourth semiconductor layer and reaching said third semiconductor layer, impurity densities of said first and second N-type high impurity density regions being higher than those of said third and fourth semiconductor layers, a first electrode and a second electrode respectively provided on said first N-type high impurity density region and on said second N-type high impurity density region; a second control electrode provided on said fifth semiconductor layer; a third N-type high impurity density region and a fourth N-type high impurity density region provided respectively on both sides of said second control electrode, said third and fourth N-type high impurity density regions extending from a surface of said fifth semiconductor layer and reaching said third semiconductor layer, impurity densities of said third and fourth N-type high impurity density regions being higher than those of said third, fourth and fifth semiconductor layers; and a third electrode and a fourth electrode respectively provided on said third N-type high impurity density region and on said fourth N-type high impurity density region.

Claim 13

A semiconductor device comprising: a substrate; a first semiconductor layer with a low impurity density provided on said substrate; a second semiconductor layer with a low impurity density provided on said first semiconductor substrate, an electron affinity of said first semiconductor layer being smaller than that of said second semiconductor layer; an N-type third semiconductor layer with a high impurity density provided on said second semiconductor layer, said third semiconductor layer acting as a channel layer; a fourth semiconductor layer with a low impurity density provided on said third semiconductor layer, the electron affinity of said fourth semiconductor layer being smaller than that of said third semiconductor layer, and said fourth semiconductor layer having a first surface portion and a second surface portion; a fifth semiconductor layer with a low impurity density provided on said second surface portion of said fourth semiconductor layer, an impurity density of said third semiconductor layer being higher than those of said first, second, fourth and fifth semiconductor layers; a first control electrode provided on said first surface portion of said fourth semiconductor layer; a first N-type high impurity density region and a second N-type high impurity density region provided respectively on both sides of said first control electrode, said first and second N-type high impurity density regions extending from said first surface portion of said fourth semiconductor layer and reaching said third semiconductor layer, impurity densities of said first and second N-type high impurity density regions being higher than those of said third and fourth semiconductor layers, a first electrode and a second electrode respectively provided on said first N-type high impurity density region and on said second N-type high impurity density region; a second control electrode provided on said fifth semiconductor layer; a third N-type high impurity density region and a fourth N-type high impurity density region provided respectively on both sides of said second control electrode, said third and fourth N-type high impurity density regions extending from a surface of said fifth semiconductor layer and reaching said third semiconductor layer, impurity densities of said third and fourth N-type high impurity density regions being higher than those of said third, fourth and fifth semiconductor layers; and a third electrode and a fourth electrode respectively provided on said third N-type high impurity density region and on said fourth N-type high impurity density region.

Claim 14

A semiconductor device as recited in claim 11, further comprising means for connecting said second electrode and said third electrode.

Claim 15

A semiconductor device as recited in claim 11, further comprising a first N-type intermediate impurtiy density region and a second N-type intermediate impurity density region with impurity densities lower than those of said first and second N-type high impurity density regions, said first and second N-type intermediate impurity regions being provided respectively between said first and second N-type high impurity density regions and said first control electrode, said first and second N-type intermediate impurity regions extending from said first surface portion of said fourth semiconductor layer and reaching said third semiconductor layer, and a third N-type intermediate impurity density region and a fourth N-type intermediate impurity density region with impurity densities lower than those third and fourth N-type high impurity density regions, said third and fourth N-type intermediate impurity regions being provided respectively between said third and fourth N-type high impurity density regions and said second control electrode, said third and fourth N-type intermediate impurity regions extending from said surface of said fifth semiconductor layer and reaching said third semiconductor layer.

Claim 16

A semiconductor device as recited in claim 11, wherein said second semiconductor layer is a high resistance buffer layer, an impurity density of said high resistance buffer layer being less than 1×10 16 cm -3 for an N-type impurity.

Claim 17

A semiconductor device as recited in claim 11, wherein said second semiconductor layer is a high resistance buffer layer, an impurity density of said high resistance buffer layer being less than 5×10 17 cm -3 for a P-type impurity.

Claim 18

A semiconductor device as recited in claim 11, wherein said impurity density of said third semiconductor layer is in the range of 5×10 17 -5×10 18 cm -3 , and said impurity density of said fourth semiconductor layer is in the range of 1×10 13 -1×10 17 cm -3 .

Claim 19

A semiconductor device as recited in claim 16, wherein a film thickness of said third semiconductor layer is in the range of 50-500 Å, and a film thickness of said fourth semiconductor layer is in the range of 50×1000 Å.

Claim 20

A semiconductor device as recited in claim 11, wherein said first semiconductor layer is an undoped aluminum gallium arsenide layer, said second semiconductor layer is an undoped gallium arsenide layer, said third semiconductor layer is an N-type gallium arsenide layer, said fourth semiconductor layer is an undoped aluminum gallium arsenide layer, said fifth semiconductor layer is an undoped gallium arsenide layer.

Claim 21

A semiconductor device comprising: a substrate; a first semiconductor layer with a low impurity density provided on said substrate; an N-type second semiconductor layer with a high impurity density provided on said first semiconductor layer, said second semiconductor layer acting as a channel layer; a third semiconductor layer with a low impurity density provided on said second semiconductor layer, the electron affinity of said third semiconductor layer being smaller than that of said second semiconductor layer; an undoped gallium arsenide layer provided on said third semiconductor layer, said undoped gallium arsenide layer having a first surface portion and a second surface portion; a fourth semiconductor layer with a low impurity density provided on said second surface portion of said undoped gallium arsenide layer, an impurity density of said second semiconductor layer being higher than those of said first, third and fourth semiconductor layers; a first contorl electrode provided on said first surface portion of said undoped gallium arsenide layer; a first N-type high impurity density region and a second N-type high impurity density region provided respectively on both sides of said first control electrode, said first and second N-type high impurity density regions extending from said first surface portion of said undoped gallium arsenide layer and reaching said second semiconductor layer, impurity densities of said first and second N-type high impurity density regions being higher than those of said second and third semiconductor layers and said undoped gallium arsenide layer; a first electrode and a second electrode respectively provided on said first N-type high impurity density region and on said second N-type high impurity density region; a second control electrode provided on said fourth semiconductor layer; a third N-type high impurity density region and a fourth N-type high impurity density region provided respectively on both sides of said second control electrode, said third and fourth N-type high impurity density regions extending from a surface of said fourth semiconductor layer and reaching said second semiconductor layer, impurity densities of said third and fourth N-type high impurity density regions being higher than those of said second, third and fourth semiconductor layers and said undoped gallium arsenide layer; and a third electrode and a fourth electrode respectively provided on said third N-type high impurity density region and on said fourth N-type high impurity density region.

Claim 22

A semiconductor device comprising: a substrate; a first semiconductor layer with a low impurity density provided on said substrate; an N-type second semiconductor layer with a high impurity density provided on said first semiconductor layer, said second semiconductor layer acting as a channel layer; a third semiconductor layer with a low impurity density provided on said second semiconductor layer, the electron affinity of said third semiconductor layer being smaller than that of said second semiconductor layer; an undoped gallium arsenide layer provided on said third semiconductor layer, said undoped gallium arsenide layer having a first surface portion and a second surface portion; a fourth semiconductor layer with a low impurity density provided on said second surface portion of said undoped gallium arsenide layer, an impurity density of said second semiconductor layer being higher than those of said first, third and fourth semiconductor layers; a first contorl electrode provided on said first surface portion of said undoped gallium arsenide layer; a first N-type high impurity density region and a second N-type high impurity density region provided respectively on both sides of said first control electrode, said first and second N-type high impurity density regions extending from said first surface portion of said undoped gallium arsenide layer and reaching said second semiconductor layer, impurity densities of said first and second N-type high impurity density regions being higher than those of said second and third semiconductor layers and said undoped gallium arsenide layer; a first electrode and a second electrode respectively provided on said first N-type high impurity density region and on said second N-type high impurity density region; a second control electrode provided on said fourth semiconductor layer; a third N-type high impurity density region and a fourth N-type high impurity density region provided respectively on both sides of said second control electrode, said third and fourth N-type high impurity density regions extending from a surface of said fourth semiconductor layer and reaching said second semiconductor layer, impurity densities of said third and fourth N-type high impurity density regions being higher than those of said second, third and fourth semiconductor layers and said undoped gallium arsenide layer; and a third electrode and a fourth electrode respectively provided on said third N-type high impurity density region and on said fourth N-type high impurity density region.

Claim 23

A semiconductor device as recited in claim 19, further comprising means for connecting said second electrode and said third electrode.

Claim 24

A semiconductor device as recited in claim 19, further comprising a fifth semiconductor layer with a low impurity density provided between said fourth semiconductor layer and said second surface portion of said undoped gallium arsenide layer, an impurity density of said fifth semiconductor layer being lower than that of said second semiconductor layer, an electron affinity of said fifth semiconductor layer being smaller than those of said fourth semiconductor layer and said undoped gallium arsenide layer, and said impurity densities of said third and fourth N-type high impurity density regions being higher than that of said fifth semiconductor layer.

Claim 25

A semiconductor device as claimed in claim 21, wherein said impurity density of said fifth semiconductor layer is in the range of 5×10 13 -5×10 17 cm -3 .

Claim 26

A semiconductor device as claimed in claim 21, wherein a film thickness of said fifth semiconductor layer is in the range of 50-500 Å.

Claim 27

A semiconductor device as recited in claim 19, wherein said first semiconductor layer is a high resistance buffer layer, an impurity density of said high resistance buffer layer being less than 1×10 16 cm -3 for an N-type impurity.

Claim 28

A semiconductor device as recited in claim 19, wherein said first semiconductor layer is a high resistance buffer layer, an impurity density of said high resistance buffer layer being less than 5×10 17 cm -3 for a P-type impurity.

Claim 29

A semiconductor device as recited in claim 19, wherein said impurity density of said second semiconductor layer is in the range of 5×10 17 -5×10 18 cm -3 said impurity density of said third semiconductor layer is in the range of 1×10 13 -1×10 17 cm -3 and said impurity density of said fourth semiconductor layer is in the range of 1×10 13 -1×10 17 cm -3 .

Claim 30

A semiconductor device as recited in claim 26, wherein a film thickness of said second semiconductor layer is in the range of 50-500 Å, a film thickness of said third semiconductor layer is in the range of 50-1000 Å, a film thickness of said undoped gallium arsenide layer is in the range of 10-500 Å, and a film thickness of said fourth semiconductor layer is in the range of 50-1000 Å.

Claim 31

A semiconductor device as recited in claim 19, wherein said first semiconductor layer is an undoped gallium arsenide layer, said second semiconductor layer is an N-type gallium arsenide layer, said third semiconductor layer is an undoped aluminum gallium arsenide layer, and said fourth semiconductor layer is an undoped gallium arsenide layer.

Claim 32

A semiconductor device as claimed in claim 19, further comprising an undoped aluminum gallium arsenide layer provided between said fourth semiconductor layer and said second surface portion of said undoped gallium arsenide layer.

Claim 33

A semiconductor device as recited in claim 19, further comprising a fifth semiconductor layer provided between said first semiconductor layer and said substrate, said fifth semiconductor layer having an impurity density lower than that of said second semiconductor layer and having an electron affinity smaller than that of said first semiconductor layer.

Claim 34

A semiconductor device as recited in claim 30, further comprising a sixth semiconductor layer provided between said fourth semiconductor layer and said second surface portion of said undoped gallium arsenide layer, said sixth semiconductor layer having an impurity density lower than that of said second semiconductor layer and having an electron affinity smaller than that of said undoped gallium arsenide layer.

Claim 35

A semiconductor device as recited in claim 31, wherein said first semiconductor layer is an undoped gallium arsenide layer, said second semiconductor layer is an N-type gallium arsenide layer, said third semiconductor layer is an undoped aluminum gallium arsenide layer, said fourth semiconductor layer is an undoped gallium arsenide layer, said fifth semiconductor layer is an undoped aluminum gallium arsenide layer, and said sixth semiconductor layer is an undoped aluminum gallium arsenide layer.

Claim 36

A semiconductor device as recited in claim 31, further comprising a seventh semiconductor layer provided between said first control electrode and said first surface portion of said undoped gallium arsenide layer, said seventh semiconductor layer having an impurity density lower than that of said second semiconductor layer and having an electron affinity smaller than that of said undoped gallium arsenide layer, said first and second N-type high impurity density regions extending from a surface of said seventh semiconductor layer, and said impurity densities of said first and second N-type high impurity density regions being higher than that of said seventh semiconductor layer.

Claim 37

A semiconductor device as recited in claim 33, wherein said first semiconductor layer is an undoped gallium arsenide layer, said second semiconductor layer is an N-type gallium arsenide layer, said third semiconductor layer is an undoped aluminum gallium arsenide layer, said fourth semiconductor layer is an undoped gallium arsenide layer, said fifth semiconductor layer is an undoped aluminum gallium arsenide layer, and said sixth and seventh semiconductor layers are undoped aluminum gallium arsenide layers.

Claim 38

A semiconductor device as recited in claim 33, wherein said impurity density of said second semiconductor layer is in the range of 5×10 17 -5×10 18 cm -3 , said impurity density of said third semiconductor layer is in the range of 1×10 13 -1×10 17 cm -3 , said impurity density of said fourth semiconductor layer is in the range of 1×10 13 -1×10 17 cm -3 , and said impurity density of said sixth and seventh semiconductor layers are in the range of 1×10 13 -1×10 17 cm -3 .

Claim 39

A semiconductor device as recited in claim 35, wherein a film thickness of said second semiconductor layer is in the range of 50-500 Å, a film thickness of said third semiconductor layer is in the range of 50-1000 Å, a film thickness of said undoped gallium arsenide layer is in the range of 10-500 Å, a film thickness of said fourth semiconductor layer is in the range of 50-1000 Å, and a film thickness of said sixth and seventh semiconductor layers are in the range of 50-500 Å.

Claim 40

A semiconductor device as recited in claim 33, wherein said first semiconductor layer is an undoped gallium arsenide layer, said second semiconductor layer is an N-type gallium arsenide layer, said third semiconductor layer is an undoped aluminum gallium arsenide layer, said fourth semiconductor layer is an undoped gallium arsenide layer, said fifth semiconductor layer is an undoped aluminum gallium arsenide layer, and said sixth and seventh semiconductor layers are undoped aluminum gallium arsenide layers.

Claim 41

A semiconductor device as recited in claim 31, wherein said impurity density of said second semiconductor layer is in the range of 5×10 17 -5×10 18 cm -3 , said impurity density of said third semiconductor layer is in the range of 1×10 13 -1×10 17 cm -3 , said impurity density of said fourth semiconductor layer is in the range of 1×10 13 -1×10 17 cm -3 , said impurity density of said sixth semiconductor layer is in the range of 1×10 13 -1×10 17 cm -3 .

Claim 42

A semiconductor device as recited in claim 38, wherein a film thickness of said second semiconductor layer is in the range of 50-500 Å, a film thickness of said third semiconductor layer is in the range of 50-1000 Å, a film thickness of said undoped gallium arsenide layer is in the range of 10-500 Å, a film thickness of said fourth semiconductor layer is in the range of 50-1000 Å, and a film thickness of said sixth semiconductor layer is in the range of 50-500 Å.

Claim 43

A semiconductor device as recited in claim 30, wherein said first semiconductor layer is an undoped gallium arsenide layer, said second semiconductor layer is an N-type gallium arsenide layer, said third semiconductor layer is an undoped aluminum gallium arsenide layer, said fourth semiconductor layer is an undoped gallium arsenide layer, and said fifth semiconductor layer is an undoped aluminum gallium arsenide layer.

Claim 44

A semiconductor device as recited in claim 19, further comprising an N-type fifth semiconductor layer with a high impurity density provided between said fourth semiconductor layer and said secoond surface portion of said undoped gallium arsenide layer, an impurity density of said fifth semiconductor layer being higher than those of said third and fourth semiconductor layer and said undoped gallium arsenide layer, an electron affinity of said fifth semiconductor layer being larger than that of said third semiconductor layer, and said impurity densities of said third and fourth N-type high impurity density regions being higher than that of said fifth semiconductor layer.

Claim 45

A semiconductor device as recited in claim 41, further comprising a sixth semiconductor layer with a low impurity density provided between said fifth semiconductor layer and said second surface portion of said undoped gallium arsenide layer, an impurity density of said sixth semiconductor layer being lower than that of said fifth semiconductor layer, and electron affinity of said sixth semiconductor layer being smaller than that of said fifth semiconductor layer, and said impurity density of said third and fourth N-type high impurity density regions being higher than that of said sixth semiconductor layer.

Claim 46

A semiconductor device as recited in claim 41, wherein said impurity density of said second semiconductor layer is in the range of 5×10 17 -5×10 18 cm -3 , said impurity density of said third semiconductor layer is in the range of 1×10 13 -1×10 17 cm -3 , said impurity density of said fifth semiconductor layer is in the range of 1×10 17 -5×10 18 cm -3 .

Claim 47

A semiconductor device as recited in claim 43, wherein a film thickness of said second semiconductor layer is in the range of 50-500 Å, a film thickness of said third semiconductor layer is in the range of 50-1000 Å, a film thickness of said undoped gallium arsenide layer is in the range of 10-500 Å, and a film thickness of said fifth semiconductor layer is in the range of 50-500 Å.

Claim 48

A semiconductor device as recited in claim 19, wherein said first semiconductor layer is an undoped gallium arsenide layer, said second semiconductor layer is an N-type gallium arsenide layer, said third semiconductor layer is an undoped aluminum gallium arsenide layer, said fourth semiconductor layer is an undoped gallium arsenide layer, and said fifth semiconductor layer is an N-type gallium arsenide layer.

Claim 49

A semiconductor device as recited in claim 45, further comprising an undoped aluminum gallium arsenide layer provided between said fifth semiconductor layer and said second surface portion of said undoped gallium arsenide layer.

Claim 50

A semiconductor device comprising: a substrate; a first semiconductor layer with a low impurity density provided on said substrate; an N-type second semiconductor layer with a high impurity density provided on said first semiconductor layer, said second semiconductor layer acting as a channel layer; a third semiconductor layer with a low impurity density provided on said second semiconductor layer, the electron affinity of said third semiconductor layer being smaller than that of said second semiconductor layer; an undoped gallium arsenide layer provided on said third semiconductor layer; a fourth semiconductor layer with a low impurity density provided on said undoped gallium arsenide layer, said fourth semiconductor layer having a first surface portion and a second surface portion, and having an electron affinity smaller than that of said undoped gallium arsenide layer; a fifth semiconductor layer with a low impurity density provided on said second surface portion of said fourth semiconductor layer, an impurity density of said second semiconductor layer being higher than those of said first, third, fourth and fifth semiconductor layers; a first control electrode provided on said first surface portion of said fourth semiconductor layer; a first N-type high impurity density region and a second N-type high impurity density region provided respectively on both sides of said first control electrode, said first and second N-type high impurity density regions extending from said first surface portion of said fourth semiconductor layer and reaching said second semiconductor layer, impurity densities of said first and second N-type high impurity density regions being higher than those of said second, third and fourth semiconductor layers and said undoped gallium arsenide layer; a first electrode and a second electrode respectively provided on said first N-type high impurity density region and on said second N-type high impurity density region; a second control electrode provided on said fifth semiconductor layer; a third N-type high impurity density region and a fourth N-type high impurity density region provided respectively on both sides of said second control electrode, said third and fourth N-type high impurity density regions extending from a surface of said fifth semiconductor layer, impurity densities of said third and fourth N-type high impurity density regions being higher than those of said second, third, fourth and fifth semiconductor layers and said undoped gallium arsenide layer; and a third electrode and a fourth electrode respectively provided on said third N-type high impurity density region and on said fourth N-type high impurity density region.

Claim 51

A semiconductor device comprising: a substrate; a first semiconductor layer with a low impurity density provided on said substrate; an N-type second semiconductor layer with a high impurity density provided on said first semiconductor layer, said second semiconductor layer acting as a channel layer; a third semiconductor layer with a low impurity density provided on said second semiconductor layer, the electron affinity of said third semiconductor layer being smaller than that of said second semiconductor layer; an undoped gallium arsenide layer provided on said third semiconductor layer; a fourth semiconductor layer with a low impurity density provided on said undoped gallium arsenide layer, said fourth semiconductor layer having a first surface portion and a second surface portion, and having an electron affinity smaller than that of said undoped gallium arsenide layer; a fifth semiconductor layer with a low impurity density provided on said second surface portion of said fourth semiconductor layer, an impurity density of said second semiconductor layer being higher than those of said first, third, fourth and fifth semiconductor layers; a first control electrode provided on said first surface portion of said fourth semiconductor layer; a first N-type high impurity density region and a second N-type high impurity density region provided respectively on both sides of said first control electrode, said first and second N-type high impurity density regions extending from said first surface portion of said fourth semiconductor layer and reaching said second semiconductor layer, impurity densities of said first and second N-type high impurity density regions being higher than those of said second, third and fourth semiconductor layers and said undoped gallium arsenide layer; a first electrode and a second electrode respectively provided on said first N-type high impurity density region and on said second N-type high impurity density region; a second control electrode provided on said fifth semiconductor layer; a third N-type high impurity density region and a fourth N-type high impurity density region provided respectively on both sides of said second control electrode, said third and fourth N-type high impurity density regions extending from a surface of said fifth semiconductor layer, impurity densities of said third and fourth N-type high impurity density regions being higher than those of said second, third, fourth and fifth semiconductor layers and said undoped gallium arsenide layer; and a third electrode and a fourth electrode respectively provided on said third N-type high impurity density region and on said fourth N-type high impurity density region.

Claim 52

A semiconductor device as recited in claim 47, further comprising means for connecting said second electrode and said third electrode.

Claim 53

A semiconductor device as recited in claim 47, wherein said impurity density of said second semiconductor layer is in the range of 5×10 17 -5×10 18 cm -3 , said impurity density of said third semiconductor layer is in the range of 1×10 13 -1×10 17 cm -3 , said impurity density of said fourth semiconductor layer is in the range of 1×10 13 -1×10 17 cm -3 and said impurity density of said fifth semiconductor layer is in the range of 1×10 13 -1×10 17 cm -3 .

Claim 54

A semiconductor device as recited in claim 49, wherein a film thickness of said second semiconductor layer is in the range of 50-500 Å, a film thickness of said third semiconductor layer is in the range of 50-1000 Å, a film thickness of said undoped gallium arsenide layer is in the range of 10-500 Å, a film thickness of said fourth semiconductor layer is in the range of 50-500 Å, and a film thickness of said fifth semiconductor layer is in the range of 50-1000 Å.

Claim 55

A semiconductor device as recited in claim 50, wherein said first semiconductor layer is an undoped gallium arsenide layer, said second semiconductor layer is an N-type gallium arsenide layer, said third semiconductor layer is an undoped aluminum gallium arsenide layer, said fourth semiconductor layer is an undoped aluminum gallium arsenide layer, and said fifth semiconductor layer is an undoped gallium arsenide layer.

Claim 56

A semiconductor device comprising: a substrate; a first semiconductor layer with a low impurity density provided on said substrate; a P-type second semiconductor layer with a high impurity density provided on said first semiconductor layer, said second semiconductor layer acting as a channel layer; a third semiconductor layer with a low impurity density provided on said second semiconductor layer, the sum of the electron affinity and the energy gap of said third semiconductor layer being larger than that of said second semiconductor layer; an undoped gallium arsenide layer provided on said third semiconductor layer, said undoped gallium arsenide layer having a first surface portion and a second surface portion; a fourth semiconductor layer with a low impurity density provided on said second surface portion of said undoped gallium arsenide layer, an impurity density of said second semiconductor layer being higher than those of said first, third and fourth semiconductor layers; a first control electrode provided on said first surface portion of said undoped gallium arsenide layer; a first P-type high impurity density region and a second P-type high impurity density region provided respectively on both sides of said first control electrode, said first and second P-type high impurity density regions extending from said first surface portion of said undoped gallium arsenide layer and reaching said second semiconductor layer, impurity densities of said first and second P-type high impurity density regions being higher than those of said second and third semiconductor layers and said undoped gallium arsenide layer; a first electrode and a second electrode respectively provided on said first P-type high impurity density region and on said second P-type high impurity density region; a second control electrode provided on said fourth semiconductor layer; a third P-type high impurity density region and a fourth P-type high impurity density region provided respectively on both sides of said second control electrode, said third and fourth P-type high impurity density regions extending from a surface of said fourth semiconductor layer and reaching said second semiconductor layer, impurity densities of said third and fourth P-type high impurity density regions being higher than those of said second, third and fourth semiconductor layers and said undoped gallium arsenide layer; and a third electrode and a fourth electrode respectively provided on said third P-type high impurity density region and on said fourth P-type high impurity density region.

Claim 57

A semiconductor device comprising: a substrate; a first semiconductor layer with a low impurity density provided on said substrate; a P-type second semiconductor layer with a high impurity density provided on said first semiconductor layer, said second semiconductor layer acting as a channel layer; a third semiconductor layer with a low impurity density provided on said second semiconductor layer, the sum of the electron affinity and the energy gap of said third semiconductor layer being larger than that of said second semiconductor layer; an undoped gallium arsenide layer provided on said third semiconductor layer, said undoped gallium arsenide layer having a first surface portion and a second surface portion; a fourth semiconductor layer with a low impurity density provided on said second surface portion of said undoped gallium arsenide layer, an impurity density of said second semiconductor layer being higher than those of said first, third and fourth semiconductor layers; a first control electrode provided on said first surface portion of said undoped gallium arsenide layer; a first P-type high impurity density region and a second P-type high impurity density region provided respectively on both sides of said first control electrode, said first and second P-type high impurity density regions extending from said first surface portion of said undoped gallium arsenide layer and reaching said second semiconductor layer, impurity densities of said first and second P-type high impurity density regions being higher than those of said second and third semiconductor layers and said undoped gallium arsenide layer; a first electrode and a second electrode respectively provided on said first P-type high impurity density region and on said second P-type high impurity density region; a second control electrode provided on said fourth semiconductor layer; a third P-type high impurity density region and a fourth P-type high impurity density region provided respectively on both sides of said second control electrode, said third and fourth P-type high impurity density regions extending from a surface of said fourth semiconductor layer and reaching said second semiconductor layer, impurity densities of said third and fourth P-type high impurity density regions being higher than those of said second, third and fourth semiconductor layers and said undoped gallium arsenide layer; and a third electrode and a fourth electrode respectively provided on said third P-type high impurity density region and on said fourth P-type high impurity density region.

Claim 58

A semiconductor device as recited in claim 52, further comprising means for connecting said second electrode and said third electrode.

Claim 59

A semiconductor device as recited in claim 53, further comprising a fifth semiconductor layer with a low impurity density provided between said fourth semiconductor layer and said second surface portion of said undoped gallium arsenide layer, an inpurity density of said fifth semiconductor layer being lower than that of said second semiconductor layer, an electron affinity of said fifth semiconductor layer being smaller than those of said fourth semiconductor layer and said undoped gallium arsenide layer, and said impurity densities of said third and fourth P-type high impurity density regions being higher than that of said fifth semiconductor layer.

Claim 60

A semiconductor device as claimed in claim 54, further comprising an undoped aluminum gallium arsenide layer provided between said fourth semiconductor layer and said second surface portion of said undoped gallium arsenide layer.

Claim 61

A semiconductor device as recited in claim 52, wherein said first semiconductor layer is an undoped gallium arsenide layer, said second semiconductor layer is a P-type Germanium layer, said third semiconductor layer is an undoped aluminum gallium arsenide layer, and said fourth semiconductor layer is an undoped gallium arsenide layer.