US5043295A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming an IC chip with self-aligned thin film resistors
Assignee: Individual
•
Filing: 1989-06-20
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Granted: 1991-08-27
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Expires: 2009-06-20
Abstract
Abstract Process of making an IC chip with thin film resistors, and IC chips made by such process, wherein a chip substrate first is covered with layers of thin film and interconnect material (with an intermediate barrier layer if needed), such layers being etched away in predetermined regions in accordance with the metal interconnect pattern, the remaining layered material being aligned vertically, and thereafter, in a section of the remaining material, etching away the interconnect material (and barrier material if used) to expose the thin film material to form a thin film resistor which is self-aligned withe the adjoining sections of interconnect conductors. The material in the predetermined regions may be etched by a dry-etch (plasma) or by a wet-etch.
Inventors
- 👤 Paul A. Ruggerio
- 👤 Cynthia E. Anderson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 01:24
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10D1/474; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/425; Y; Y10; Y10S; Y10S148/00; Y10S148/136
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
149 words
A process of forming an IC chip with at least one thin film resistor comprising: depositing a layer of thin film material on a predetermined area of a substrate; depositing over said thin film material a layer of interconnect material arranged to establish electrically-conductive connection to the thin film material throughout said predetermined area thereof; removing both said thin film and interconnect layers in predetermined regions of said area while leaving at least a part of the remaining layers aligned vertically, the remaining interconnect material defining an interconnect pattern for said IC chip; said remaining part of said layers including at least one segment with thin film material to be developed as a resistor; and removing all material above the layer of thin film material in an intermediate section of said one segment to present the exposed thin film material as a resistor between adjoining sections of said segment.
Claim 2
Dependent Claim
149 words
A process of forming an IC chip with at least one thin film resistor comprising: depositing a layer of thin film material on a predetermined area of a substrate; depositing over said thin film material a layer of interconnect material arranged to establish electrically-conductive connection to the thin film material throughout said predetermined area thereof; removing both said thin film and interconnect layers in predetermined regions of said area while leaving at least a part of the remaining layers aligned vertically, the remaining interconnect material defining an interconnect pattern for said IC chip; said remaining part of said layers including at least one segment with thin film material to be developed as a resistor; and removing all material above the layer of thin film material in an intermediate section of said one segment to present the exposed thin film material as a resistor between adjoining sections of said segment.
Claim 3
Dependent Claim
24 words
The process of claim 1, wherein said thin film and interconnect layers are removed in said predetermined regions by applications of a dry etch.
Claim 4
Dependent Claim
41 words
The process of claim 2, including the step of depositing a layer of barrier material between said thin film material and said interconnect material, said barrier material being removed in said predetermined regions simultaneously with said thin film and interconnect layers.
Claim 5
Dependent Claim
13 words
The process of claim 3, wherein said thin film material is Silicon Chrome.
Claim 6
Dependent Claim
11 words
The process of claim 3, wherein said barrier material is TiW.
Claim 7
Dependent Claim
16 words
The process of claim 2, wherein said dry etch comprises a chlorinated gas in a plasma.
Claim 8
Dependent Claim
21 words
The process of claim 1, wherein said interconnect layer is removed in said predetermined regions by application of a wet etch.
Claim 9
Dependent Claim
39 words
The process of claim 7, including the step of depositing a layer of barrier material between said thin film layer and said interconnect material, said barrier material being removed from said predetermined regions by application of a wet etch.
Claim 10
Dependent Claim
20 words
The process of claim 8, wherein the wet etch applications comprise PAN etch followed by H 2 O 2 .
Claim 11
Dependent Claim
22 words
The process of claim 9, wherein said thin film material is removed from said predetermined regions by application of a plasma etch.
Claim 12
Dependent Claim
175 words
A process of forming an IC chip with at least one thin film resistor comprising: depositing a layer of thin film material on a predetermined area of a substrate; depositing over said thin film material a layer of interconnect material arranged to establish electrically-conductive connection to the thin film material therebeneath; removing both said thin film and interconnect layers in predetermined regions of said predetermined area, the removal being carried out by a process which provides that the side edges of the remaining layers are aligned vertically, the remaining interconnect material defining an interconnect pattern for said IC chip; said remaining layers including at least one segment wherein at least part of the thin film material is to be developed as a resistor forming part of the circuit of said IC chip; and removing all material above the layer of thin film material in an intermediate section of said one segment to present the exposed thin film material without any interconnect directly thereabove, thereby to provide said resistor between spaced-apart sections of said one segment.
Claim 13
Dependent Claim
175 words
A process of forming an IC chip with at least one thin film resistor comprising: depositing a layer of thin film material on a predetermined area of a substrate; depositing over said thin film material a layer of interconnect material arranged to establish electrically-conductive connection to the thin film material therebeneath; removing both said thin film and interconnect layers in predetermined regions of said predetermined area, the removal being carried out by a process which provides that the side edges of the remaining layers are aligned vertically, the remaining interconnect material defining an interconnect pattern for said IC chip; said remaining layers including at least one segment wherein at least part of the thin film material is to be developed as a resistor forming part of the circuit of said IC chip; and removing all material above the layer of thin film material in an intermediate section of said one segment to present the exposed thin film material without any interconnect directly thereabove, thereby to provide said resistor between spaced-apart sections of said one segment.
Claim 14
Dependent Claim
24 words
The process of claim 11, wherein said thin film and interconnect layers are removed in said predetermined regions by application of a dry etch.
Claim 15
Dependent Claim
44 words
The process of claim 12, including the step of depositing a layer of barrier material between said thin film material and said interconnect material, said barrier material being removed in said predetermined regions simultaneously with said removal of said thin film and interconnect layers.
Claim 16
Dependent Claim
21 words
The process of claim 11, wherein said interconnect layer is removed from said predetermined regions by application of a wet etch.
Claim 17
Dependent Claim
22 words
The process of claim 14, wherein said thin film material is removed from said predetermined regions by application of a plasma etch.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-08-26 | 1995-02-25 | 1995-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-08-26 | 1999-02-25 | 1999-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-08-26 | 2003-02-25 | 2003-08-27 | $7700.00 | Window Closed / Lapsed |