Insulator structure for amorphous silicon thin-film transistors

Claim 2

A semiconductor device comprising: a substrate; a gate electrode disposed on said substrate; a first layer of silicon nitride disposed on said substrate and over said gate electrode, said first silicon nitride layer having a first silicon-to-nitrogen (Si:N) concentration ratio selected to provide optimum structural characteristics to said semiconductor device and having a first optical index corresponding to said first selected concentration ratio; a second layer of silicon nitride disposed on said first silicon nitride layer, said second silicon nitride layer having a second silicon-to-nitrogen (Si:N) concentration ratio selected to provide optimum electrical characteristics to said semiconductor device and having a second optical index corresponding to said second selected concentration ratio; said first optical index being greater than said second optical index; a first layer of amorphous silicon disposed on said second silicon nitride layer, a second layer of amorphous silicon disposed on said first silicon layer and doped to have a chosen conductivity; at least said second silicon layer being patterned to form a drain region and a source region, each of said regions partially overlying said gate electrode to cause a conductive channel between said source and drain regions through a portion of said first silicon layer lying therebetween when a voltage of proper polarity and magnitude is applied to said gate electrode relative to said source region; a source electrode in electrical contact with said source region; and a drain electrode in electrical contact with said drain region.

Claim 3

The device of claim 1 wherein said second Si:N ratio is selected to cause said second silicon nitride layer to have an optical index of about 1.87 at a wavelength of 6328 angstrom units when said second layer is deposited at a temperature between about 250° C. and about 300° C.

Claim 4

The device of claim 2 wherein said second silicon nitride layer has a thickness less than about 200 angstroms.

Claim 5

The device of claim 1 wherein said first Si:N ratio is selected to cause said first silicon layer to have an optical index at a wavelength of 6328 angstrom units not less than about 1.90 when said first layer is deposited at a temperature between about 250° C. and about 300° C.

Claim 6

The device of claim 4 wherein said first silicon nitride layer has a thickness between about 1000-3000 angstroms.

Claim 7

The device of claim 1 wherein said first silicon nitride layer has a higher dielectric strength and a lower etch rate than said second silicon nitride layer.

Claim 8

The device of claim 1 wherein said second silicon nitride layer provides high charge mobility and threshold voltage stability relative to said first silicon nitride layer when said device is operational.

Claim 9

A cell structure for liquid crystal displays, comprising: a substrate; a gate metallization layer disposed on said substrate and patterned to form a scan line and a gate electrode of a resulting thin-film transistor (TFT); a first layer of silicon nitride disposed on said substrate and over said gate metallization layer and having a first silicon-to-nitrogen (Si:N) concentration ratio selected to provide optimum structural characteristics to said resulting TFT and having a first optical index corresponding to said first selected concentration ratio; an island structure forming a remaining portion of said resulting TFT and comprising: (a) a second layer of silicon nitride disposed on said first silicon nitride layer and having a second silicon-to-nitrogen (Si:N) concentration ratio selected to provide optimum electrical characteristics to said resulting TFT and having a second optical index corresponding to said second selected concentration ratio; (b) a first layer of amorphous silicon disposed on said second silicon nitride layer; (c) a second layer of amorphous silicon disposed on said first silicon layer and doped to have a chosen conductivity; at least said second silicon layer being patterned to form a drain region and a source region, each of said regions partially overlying said gate electrode to cause a conductive channel between said source and drain regions through a portion of said first silicon layer when a voltage of proper polarity and magnitude is applied to said gate electrode relative to said source region; said first optical index being greater than said second optical index; a pixel electrode disposed on said first silicon nitride layer adjacent to said island structure; and a source/drain metallization layer disposed over said island structure, said first silicon nitride layer and partially over said pixel electrode, said source/drain metallization layer being patterned to connect one of said source and drain regions to said pixel electrode and the other of said source and drain regions to a data address line.

Claim 10

A cell structure for liquid crystal displays, comprising: a substrate; a gate metallization layer disposed on said substrate and patterned to form a scan line and a gate electrode of a resulting thin-film transistor (TFT); a first layer of silicon nitride disposed on said substrate and over said gate metallization layer and having a first silicon-to-nitrogen (Si:N) concentration ratio selected to provide optimum structural characteristics to said resulting TFT and having a first optical index corresponding to said first selected concentration ratio; an island structure forming a remaining portion of said resulting TFT and comprising: (a) a second layer of silicon nitride disposed on said first silicon nitride layer and having a second silicon-to-nitrogen (Si:N) concentration ratio selected to provide optimum electrical characteristics to said resulting TFT and having a second optical index corresponding to said second selected concentration ratio; (b) a first layer of amorphous silicon disposed on said second silicon nitride layer; (c) a second layer of amorphous silicon disposed on said first silicon layer and doped to have a chosen conductivity; at least said second silicon layer being patterned to form a drain region and a source region, each of said regions partially overlying said gate electrode to cause a conductive channel between said source and drain regions through a portion of said first silicon layer when a voltage of proper polarity and magnitude is applied to said gate electrode relative to said source region; said first optical index being greater than said second optical index; a pixel electrode disposed on said first silicon nitride layer adjacent to said island structure; and a source/drain metallization layer disposed over said island structure, said first silicon nitride layer and partially over said pixel electrode, said source/drain metallization layer being patterned to connect one of said source and drain regions to said pixel electrode and the other of said source and drain regions to a data address line.

Claim 11

The cell structure of claim 8 wherein said second Si:N ratio is selected to cause said second silicon nitride layer to have an optical index of about 1.87 at a wavelength of 6328 angstrom units when said second layer is deposited at a temperature between about 250° C. and about 300° C.

Claim 12

The cell structure of claim 9 wherein said second silicon nitride layer has a thickness less than about 200 angstroms.

Claim 13

The cell structure of claim 8 wherein said first Si:N ratio is selected to cause said first silicon nitride layer to have an optical index at a wavelength of 6328 angstrom units not less than about 1.90 when said first layer is deposited at a temperature between about 250° and 300° C.

Claim 14

The cell structure of claim 11 wherein said first silicon nitride layer has a thickness between about 1000-3000 angstroms.

Claim 15

The cell structure of claim 8 wherein said first silicon nitride layer has a higher dielectric strength and a lower etch rate than said second silicon nitride layer.

Claim 16

The cell structure of claim 8 wherein when said device is operational said second silicon nitride layer provides higher charge mobility and threshold voltage stability than a device having only said first silicon nitride layer.