Thin film transistor

Abstract

Abstract PURPOSE:To contrive reduction in the lattice distortion generated in the vicinity of the interface of a gate insulating film and a semiconductor by a method wherein a gate insulating film is composed of laminated structure of gate insulating film having both tensile stress and compressive stress, and the internal stress in the direction same as a semiconductor layer is formed on the whole. CONSTITUTION:A gate electrode G is provided on the insulated substrate 1 on which a pattern is formed, and a nitride film (stress of delta1 and film thickness of d1) having the compressive stress of 2X10<10>dynes/cm<2>, for example, is provided as the first gate insulating film 4. A nitride film (stress of delta2 and film thickness of d2) having the tensile stress of 3X10<9>dynes/cm<2>, for example, is provided as the second gate insulating film 42. An amorphous silicon film (pressure delta3 and film thickness of d3) having compressive stress of 7X10<9>dynes/cm<2>, for example, is provided as a semiconductor layer 3. Then, the film thickness d1 and d2, which satisfy the formula of delta1.d1+delta2.d2=delta3.d3 are determined. Subsequently, ohmic contact films 2s and 2d are formed, and then source and drain electrodes S and D films are formed. The entire internal stress of a gate insulating film 4 is formed in the same direction as a semiconductor layer 3.

Inventors

• 👤 Koichi Hiranaka
• 👤 Tadahisa Yamaguchi

Bibliographic Details