Power semiconductor device

Claim 1

A power semiconductor device comprising: a layered first insulating region formed adjacent and below a first major surface of a single crystalline semiconductor layer; a first conductive layer formed on said first insulating region and having the same conductivity type as that of said semiconductor layer; a layered second insulating region, formed on said first conductive layer; a vertical power transistor having said semiconductor layer as one of its components and formed on and below the first major surface of said semiconductor layer and laterally displaced from said first insulating region, said power transistor having a control input terminal; a third insulating region for dielectrically isolating said first conductive layer from a laterally adjacent portion of said semiconductor layer; and a first complementary MIS inverter formed on said second insulating region, for controlling said vertical power transistor, said first complementary MIS inverter having a source region and a drain region in contact with said second insulating region, said drain region being coupled to said control input terminal of said power transistor, and means for maintaining said source region and said first conductive layer at a predetermined bias to prevent formation of a back channel of said first complementary MIS inverter.