Latch-up preventer for cmos transistor

Abstract

Abstract PURPOSE:To prevent the generation of latch-up phenomenon by a method wherein the gate passing through a guard ring in the depth direction constitutes a MOS transistor including a well as the source and the guard ring as the drain. CONSTITUTION:An an annular moat 22 is located at the center of the guard ring 21 and is deeper than the guard ring 21. The moat 22 is embedded with a plurality of poly Si gates 23 at some intervals, and all the gates 23 are connected to the guard ring 21 and joined with one another to poly Si connection lines 24. Each gate 23 is insulated from the substrate 1 and the well 2 by an Si dioxide layer 25 in the moat 22. The Si gates 23 are grounded (VSS). A back bias generator 27 is connected to the guard ring 21, and this generator 27 is made to produce voltage lower than the negative value impressed on the drain region 5, which voltage is impressed on the guard ring 21.

Inventors

• 👤 Seiji Hashimoto
• 👤 征史 橋本

Bibliographic Details