Amorphous silicon thin film transistor array substrate and method for producing the same

Claim 3

In a method for producing an amorphous silicon thin film transistor array substrate having a plurality of amorphous silicon thin film transistors formed on an insulating substrate, each of said amorphous silicon thin film transistors having a gate electrode formed on said insulating substrate, a gate insulating layer covering said gate electrode, an amorphous silicon layer formed on said gate insulating layer, and source and drain electrodes formed on said amorphous silicon layer, wherein said method comprises: forming gate electrodes on an insulating substrate and simultaneously forming gate wiring on said insulating substrate for connecting said gate electrodes to one another, said gate wiring having a gate terminal adjacent an edge of said insulating substrate for connection to an external circuit, forming a gate insulating layer on substantially the entire surface of said insulating substrate, forming an amorphous silicon layer on said gate insulating layer, for forming said amorphous silicon thin film transistors, forming source and drain electrodes on said amorphous silicon layer, and forming source wiring for connecting said source electrodes to one another, said source wiring having a source terminal adjacent an edge of said insulating substrate for connection to an external circuit, the improvement wherein said step of forming a gate insulating layer comprises forming said gate insulating layer except on said gate terminal, and said step of forming said source wiring comprises forming said source terminal entirely on said gate insulating layer, whereby said source terminal is at substantially the same level as the portion of the source wiring adjacent thereto.

Claim 4

In a method for producing an amorphous silicon thin film transistor array substrate having a plurality of amorphous silicon thin film transistors formed on an insulating substrate, each of said amorphous silicon thin film transistors having a gate electrode formed on said insulating substrate, a gate insulating layer covering said gate electrode, an amorphous silicon layer formed on said gate insulating layer, and source and drain electrodes formed on said amorphous silicon layer, wherein said method comprises: forming gate electrodes on an insulating substrate and simultaneously forming gate wiring on said insulating substrate for connecting said gate electrodes to one another, said gate wiring having a gate terminal adjacent an edge of said insulating substrate for connection to an external circuit, forming a gate insulating layer on substantially the entire surface of said insulating substrate, forming an amorphous silicon layer on said gate insulating layer, for forming said amorphous silicon thin film transistors, forming source and drain electrodes on said amorphous silicon layer, and forming source wiring for connecting said source electrodes to one another, said source wiring having a source terminal adjacent an edge of said insulating substrate for connection to an external circuit, the improvement wherein said step of forming a gate insulating layer comprises forming said gate insulating layer except on said gate terminal, and said step of forming said source wiring comprises forming said source terminal entirely on said gate insulating layer, whereby said source terminal is at substantially the same level as the portion of the source wiring adjacent thereto.