Programmable logic array with reduced power consumption

Claim 2

A programmable logic array comprising: a programmable logic array precharged and discharged in synchronism with a clock signal supplied thereto and outputting an operation result with respect to input data supplied thereto; and holding and switching means connected to said programmable logic array, said holding and switching means for holding the programmable logic array in a precharged state when said programmable logic array is not selected by setting said clock signal to a fixed level and said holding and switching means for switching said programmable logic array to a discharged state when said programmable logic array is selected by supplying said clock signal to said programmable logic array, so that said programmable logic array is discharged based on contents of said input data when selected and therein generates said operation result with respect to said input data.

Claim 3

A programmable logic array as claimed in claim 1, wherein said programmable logic array is divided into a plurality of sub-programmable logic arrays, and said holding and switching means is provided for each of the plurality of sub-programmable logic arrays.

Claim 4

A programmable logic array as claimed in claim 2, wherein said holding and switching means provided for each of the sub-programmable logic arrays comprises decoder means for decoding said input data to determined whether or not a corresponding sub-programmable logic array, which is one of said sub-programmable logic arrays, is selected, and clock control means, connected to said decoder means, for supplying the corresponding sub-programmable logic array with said clock signal only when the corresponding sub-programmable logic array is selected.

Claim 5

A programmable logic array as claimed in claim 3, wherein said decoder means decodes a part of said input data.

Claim 6

A programmable logic array as claimed in claim 2, wherein said programmable logic array is divided into the plurality of sub-programmable logic arrays, depending on functions achieved by said programmable logic array.

Claim 7

A programmable logic array as claimed in claim 1, wherein said programmable logic array is alternately switched to said discharged state and precharged state in synchronism with said clock signal only when said programmable logic array is selected.

Claim 8

A programmable logic array comprising: a programmable logic array precharged and discharged in synchronism with a clock signal supplied thereto and outputting an operation result with respect to input data supplied thereto, said programmable logic array is divided into a plurality of sub-programmable logic arrays; and holding and switching means connected to said programmable logic array, said holding and switching means for holding the programmable logic array in a precharged state when said programmable logic array is not selected by setting said clock signal to a fixed level and said holding and switching means for switching said programmable logic array to a discharged state when said programmable logic array is selected by supplying said clock signal to said programmable logic array, so that said programmable logic array is discharged based on contents of said input data when selected and therein generates said operation result with respect to said input data, said holding and switching means is provided for each of the plurality of sub-programmable logic arrays, and comprises decoder means for decoding said input data to determining whether or not a corresponding sub-programmable logic array, which is one of said sub-programmable logic arrays, is selected, and clock control means, connected to said decoder means, for supplying the corresponding sub-programmable logic array with said clock signal only when the corresponding sub-programmable logic array is selected during a time where a read signal defining a timing for outputting said operation result is supplied to said related clock control means.

Claim 9

A programmable logic array comprising: a programmable logic array precharged and discharged in synchronism with a clock signal supplied thereto and outputting an operation result with respect to input data supplied thereto, said programmable logic array is divided into a plurality of sub-programmable logic arrays; and holding and switching means connected to said programmable logic array, said holding and switching means for holding the programmable logic array in a precharged state when said programmable logic array is not selected by setting said clock signal to a fixed level and said holding and switching means for switching said programmable logic array to a discharged state when said programmable logic array is selected by supplying said clock signal to said programmable logic array, so that said programmable logic array is discharged based on contents of said input data when selected and therein generates said operation result with respect to said input data, said holding and switching means is provided for each of the plurality of sub-programmable logic arrays, and comprises decoder means for decoding said input data to determining whether or not a corresponding sub-programmable logic array, which is one of said sub-programmable logic arrays, is selected, and clock control means, connected to said decoder means, for supplying the corresponding sub-programmable logic array with said clock signal only when the corresponding sub-programmable logic array is selected during a time where a read signal defining a timing for outputting said operation result is supplied to said related clock control means.

Claim 10

A programmable logic array as claimed in claim 7, wherein said related clock control means comprises an NAND gate having first and second input terminals supplied with an external clock signal and said read signal, respectively, a third input terminal connected to the corresponding decoder means, and an output terminal through which said clock signal, derived from said external clock signal and said read signal, is output.

Claim 11

A programmable logic array comprising: a programmable logic array precharged and discharged in synchronism with a clock signal supplied thereto and outputting an operation result with respect to input data supplied thereto, said programmable logic array is divided into a plurality of sub-programmable logic arrays, the plurality of sub-programmable logic arrays have output terminals through which corresponding operation results are output, and said output terminals of the plurality of sub-programmable logic arrays are coupled to corresponding transistors which are mutually connected to thereby form a wired OR logic output; and holding and switching means connected to said programmable logic array, said holding and switching means for holding the programmable logic array in a precharged state when said programmable logic array is not selected by setting said clock signal to a fixed level and said holding and switching means for switching said programmable logic array to a discharged state when said programmable logic array is selected by supplying said clock signal to said programmable logic array, so that said programmable logic array is discharged based on contents of said input data when selected and therein generates said operation result with respect to said input data, said holding and switching means is provided for each of the plurality of sub-programmable logic arrays.

Claim 12

A programmable logic array comprising: a programmable logic array precharged and discharged in synchronism with a clock signal supplied thereto and outputting an operation result with respect to input data supplied thereto, said programmable logic array is divided into a plurality of sub-programmable logic arrays, the plurality of sub-programmable logic arrays have output terminals through which corresponding operation results are output, and said output terminals of the plurality of sub-programmable logic arrays are coupled to corresponding transistors which are mutually connected to thereby form a wired OR logic output; and holding and switching means connected to said programmable logic array, said holding and switching means for holding the programmable logic array in a precharged state when said programmable logic array is not selected by setting said clock signal to a fixed level and said holding and switching means for switching said programmable logic array to a discharged state when said programmable logic array is selected by supplying said clock signal to said programmable logic array, so that said programmable logic array is discharged based on contents of said input data when selected and therein generates said operation result with respect to said input data, said holding and switching means is provided for each of the plurality of sub-programmable logic arrays.

Claim 13

A programmable logic array comprising: a programmable logic array precharged and discharged in synchronism with a clock signal supplied thereto and outputting an operation result with respect to input data supplied thereto, said programmable logic array is divided into a plurality of sub-programmable logic arrays; holding and switching means connected to said programmable logic array, said holding and switching means for holding the programmable logic array in a precharged state when said programmable logic array is not selected by setting said clock signal to a fixed level and said holding and switching means for switching said programmable logic array to a discharged state when said programmable logic array is selected by supplying said clock signal to said programmable logic array, so that said programmable logic array is discharged based on contents of said input data when selected and therein generates said operation result with respect to said input data, said holding and switching means is provided for each of the plurality of sub-programmable logic arrays; and precharge means for precharging a wired OR logic output during a time when said programmable logic array composed of the plurality of sub-programmable logic arrays is not selected.

Claim 14

A programmable logic array comprising: a programmable logic array precharged and discharged in synchronism with a clock signal supplied thereto and outputting an operation result with respect to input data supplied thereto, said programmable logic array is divided into a plurality of sub-programmable logic arrays; holding and switching means connected to said programmable logic array, said holding and switching means for holding the programmable logic array in a precharged state when said programmable logic array is not selected by setting said clock signal to a fixed level and said holding and switching means for switching said programmable logic array to a discharged state when said programmable logic array is selected by supplying said clock signal to said programmable logic array, so that said programmable logic array is discharged based on contents of said input data when selected and therein generates said operation result with respect to said input data, said holding and switching means is provided for each of the plurality of sub-programmable logic arrays; and precharge means for precharging a wired OR logic output during a time when said programmable logic array composed of the plurality of sub-programmable logic arrays is not selected.

Claim 15

A programmable logic array comprising: a programmable logic array precharged and discharged in synchronism with a clock signal supplied thereto and outputting an operation result with respect to input data supplied thereto, said programmable logic array is divided into a plurality of sub-programmable logic arrays wherein the plurality of sub-programmable logic arrays are periodically selected; and holding and switching means connected to said programmable logic array, said holding and switching means for holding the programmable logic array in a precharged state when said programmable logic array is not selected by setting said clock signal to a fixed level and said holding and switching means for switching said programmable logic array to a discharged state when said programmable logic array is selected by supplying said clock signal to said programmable logic array, so that said programmable logic array is discharged based on contents of said input data when selected and therein generates said operation result with respect to said input data, said holding and switching means is provided for each of the plurality of sub-programmable logic arrays.

Claim 16

A programmable logic array comprising: a programmable logic array precharged and discharged in synchronism with a clock signal supplied thereto and outputting an operation result with respect to input data supplied thereto, said programmable logic array is divided into a plurality of sub-programmable logic arrays wherein the plurality of sub-programmable logic arrays are periodically selected; and holding and switching means connected to said programmable logic array, said holding and switching means for holding the programmable logic array in a precharged state when said programmable logic array is not selected by setting said clock signal to a fixed level and said holding and switching means for switching said programmable logic array to a discharged state when said programmable logic array is selected by supplying said clock signal to said programmable logic array, so that said programmable logic array is discharged based on contents of said input data when selected and therein generates said operation result with respect to said input data, said holding and switching means is provided for each of the plurality of sub-programmable logic arrays.

Claim 17

A programmable logic array comprising: a programmable logic array precharged and discharged in synchronism with a clock signal supplied thereto and outputting an operation result with respect to input data supplied thereto; and holding and switching means connected to said programmable logic array, said holding and switching means for holding the programmable logic array in a precharged state when said programmable logic array is not selected by setting said clock signal to a fixed level and said holding and switching means for switching said programmable logic array to a discharged state when said programmable logic array is selected by supplying said clock signal to said programmable logic array, so that said programmable logic array is discharged based on contents of said input data when selected and therein generates said operation result with respect to said input data, said holding and switching means generates a fixed voltage of a high level when said programmable logic array is not selected.

Claim 18

A programmable logic array comprising: a programmable logic array precharged and discharged in synchronism with a clock signal supplied thereto and outputting an operation result with respect to input data supplied thereto; and holding and switching means connected to said programmable logic array, said holding and switching means for holding the programmable logic array in a precharged state when said programmable logic array is not selected by setting said clock signal to a fixed level and said holding and switching means for switching said programmable logic array to a discharged state when said programmable logic array is selected by supplying said clock signal to said programmable logic array, so that said programmable logic array is discharged based on contents of said input data when selected and therein generates said operation result with respect to said input data, said holding and switching means generates a fixed voltage of a high level when said programmable logic array is not selected.

Claim 19

A programmable logic array comprising: a programmable logic array precharged and discharged in synchronism with a clock signal supplied thereto and outputting an operation result with respect to input data supplied thereto; and holding and switching means connected to said programmable logic array, said holding and switching means for holding the programmable logic array in a precharged state when said programmable logic array is not selected by setting said clock signal to a fixed level and said holding and switching means for switching said programmable logic array to a discharged state when said programmable logic array is selected by supplying said clock signal to said programmable logic array, so that said programmable logic array is discharged based on contents of said input data when selected and therein generates said operation result with respect to said input data, wherein said holding and switching means receives an external clock signal and a read signal, and wherein when said read signal is supplied thereto, said holding and switching means supplies said programmable logic array with said external clock signal as said clock signal, and therein switches said programmable logic array to the discharged state where said programmable logic array is discharged based on the contents of said input data, and said holding and switching means holds said programmable logic array in the precharged state when no signal is supplied to said holding and switching means.

Claim 20

A programmable logic array comprising: a programmable logic array precharged and discharged in synchronism with a clock signal supplied thereto and outputting an operation result with respect to input data supplied thereto; and holding and switching means connected to said programmable logic array, said holding and switching means for holding the programmable logic array in a precharged state when said programmable logic array is not selected by setting said clock signal to a fixed level and said holding and switching means for switching said programmable logic array to a discharged state when said programmable logic array is selected by supplying said clock signal to said programmable logic array, so that said programmable logic array is discharged based on contents of said input data when selected and therein generates said operation result with respect to said input data, wherein said holding and switching means receives an external clock signal and a read signal, and wherein when said read signal is supplied thereto, said holding and switching means supplies said programmable logic array with said external clock signal as said clock signal, and therein switches said programmable logic array to the discharged state where said programmable logic array is discharged based on the contents of said input data, and said holding and switching means holds said programmable logic array in the precharged state when no signal is supplied to said holding and switching means.

Claim 21

A programmable logic array comprising: a programmable logic array precharged and discharged in synchronism with a clock signal supplied thereto and outputting an operation result with respect to input data supplied thereto, said programmable logic array is divided into a plurality of sub-programmable logic arrays; and holding and switching means connected to said programmable logic array, said holding and switching means for holding the programmable logic array in a precharged state when said programmable logic array is not selected by setting said clock signal to a fixed level and said holding and switching means for switching said programmable logic array to a discharged state when said programmable logic array is selected by supplying said clock signal to said programmable logic array, so that said programmable logic array is discharged based on contents of said input data when selected and therein generates said operation result with respect to said input data, said holding and switching means is provided for each of the plurality of sub-programmable logic arrays and comprises decoder means for decoding said input data to determining whether or not a corresponding sub-programmable logic array, which is one of said sub-programmable logic arrays, is selected, and clock control means, connected to said decoder means, for supplying the corresponding sub-programmable logic array with said clock signal only when the corresponding sub-programmable logic array is selected, wherein said input data is composed of a plurality of bits, and wherein said decoder means comprises inverters individually provided for said plurality of bits and each having an input terminal supplied with corresponding one of said bits and an output terminal, and an AND gate having input terminals respectively connected to the output terminals of said inverters and an output terminal connected to said clock control means.

Claim 22

A programmable logic array comprising: a programmable logic array precharged and discharged in synchronism with a clock signal supplied thereto and outputting an operation result with respect to input data supplied thereto, said programmable logic array is divided into a plurality of sub-programmable logic arrays; and holding and switching means connected to said programmable logic array, said holding and switching means for holding the programmable logic array in a precharged state when said programmable logic array is not selected by setting said clock signal to a fixed level and said holding and switching means for switching said programmable logic array to a discharged state when said programmable logic array is selected by supplying said clock signal to said programmable logic array, so that said programmable logic array is discharged based on contents of said input data when selected and therein generates said operation result with respect to said input data, said holding and switching means is provided for each of the plurality of sub-programmable logic arrays and comprises decoder means for decoding said input data to determining whether or not a corresponding sub-programmable logic array, which is one of said sub-programmable logic arrays, is selected, and clock control means, connected to said decoder means, for supplying the corresponding sub-programmable logic array with said clock signal only when the corresponding sub-programmable logic array is selected, wherein said input data is composed of a plurality of bits, and wherein said decoder means comprises inverters individually provided for said plurality of bits and each having an input terminal supplied with corresponding one of said bits and an output terminal, and an AND gate having input terminals respectively connected to the output terminals of said inverters and an output terminal connected to said clock control means.