Device for timing interrupt acknowledge cycles

Claim 2

A computer peripheral chip compatible with Central Processing Units (CPU's) operating with different clock speeds, said peripheral connected through a system but with a CPU timed by a CPU clock, wherein an interrupt acknowledge cycle takes place by the CPU issuing an interrupt acknowledge signal followed by a leading edge of a read signal to the peripheral resulting in the peripheral putting a valid interrupt vector on the system but after a first period of time relative to the leading edge of the read signal, and the CPU issuing a trailing edge of the read signal after a second period of time relative to the leading edge of the read signal, said trailing edge being used to read the interrupt vector from the system bus, the improvement including a device within the peripheral chip which allows a valid interrupt vector to be read under different CPU clock speeds, comprising: an analog RC circuit for providing a peripheral clock signal independent of the CPU clock; a plurality of daisy-chained flip-flops for clocking the peripheral clock signal therethrough in order to slow down the peripheral clock signal to have a period equal to a predetermined duration of time, said predetermined duration of time being use to extend the second period of time beyond the first period of time; and means responsive to the leading edge of the read signal for asserting a control signal therefrom to suspend the operation of the CPU for said predetermined duration of time, thereby extending said second period of time until it is greater than said first period of time such that a valid interrupt vector is read by the CPU.

Claim 3

A computer peripheral chip compatible with Central Processing Units (CPU's) operating with different clock speeds, said peripheral connected through a system bus with a CPU timed by a CPU clock, wherein an interrupt acknowledge cycle takes place by the CPU issuing an interrupt acknowledge signal followed by a leading edge of a read signal to the peripheral resulting in the peripheral putting a valid interrupt vector on the system bus after a first period of time relative to the leading edge of the read signal, and the CPU suspending the operation of the CPU from the leading edge of the read signal until re-activated by the assertion of a control signal to resume issuing of a trailing edge of the read signal after a second period of time relative to the leading edge of the read signal, said trailing edge being used to read the interrupt vector from the system but, the improvement including a device within the peripheral chip which allows a valid interrupt vector to be read under different CPU clock speeds, comprising: an analog RC circuit for providing a peripheral clock signal independent of the CPU clock; a plurality of daisy-chained flip-flops for clocking the peripheral clock signal therethrough in order to slow down the peripheral clock signal to have a period equal to a predetermined duration of time, said predetermined duration of time being use to extend the second period of time beyond the first period of time; and means responsive to the leading edge of the read signal for starting the predetermined duration of time therefrom and for asserting a control signal at the end of the predetermined duration of time to re-activate the CPU, thereby extending said second period of time until it is greater than said first period of time such that a valid interrupt vector is read by the CPU.

Claim 4

A computer peripheral chip compatible with Central Processing Units (CPU's) operating with different clock speeds, said peripheral connected through a system bus with a CPU timed by a CPU clock, wherein an interrupt acknowledge cycle takes place by the CPU issuing an interrupt acknowledge signal followed by a leading edge of a read signal to the peripheral resulting in the peripheral putting a valid interrupt vector on the system bus after a first period of time relative to the leading edge of the read signal, and the CPU suspending the operation of the CPU from the leading edge of the read signal until re-activated by the assertion of a control signal to resume issuing of a trailing edge of the read signal after a second period of time relative to the leading edge of the read signal, said trailing edge being used to read the interrupt vector from the system but, the improvement including a device within the peripheral chip which allows a valid interrupt vector to be read under different CPU clock speeds, comprising: an analog RC circuit for providing a peripheral clock signal independent of the CPU clock; a plurality of daisy-chained flip-flops for clocking the peripheral clock signal therethrough in order to slow down the peripheral clock signal to have a period equal to a predetermined duration of time, said predetermined duration of time being use to extend the second period of time beyond the first period of time; and means responsive to the leading edge of the read signal for starting the predetermined duration of time therefrom and for asserting a control signal at the end of the predetermined duration of time to re-activate the CPU, thereby extending said second period of time until it is greater than said first period of time such that a valid interrupt vector is read by the CPU.