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US5031173A
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Decoder for added asynchronous bit sequences
Assignee: Unisys Corp
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Filing: 1989-08-15
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Granted: 1991-07-09
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Expires: 2009-08-15
Abstract
Abstract A composite signal is formed by simultaneously transmitting multiple asynchronous data bit sequences, that are coded with respective spreading codes, in a single channel; and a circuit is provided which decodes any bit b(x) in that composite signal. This circuit includes a set of filters which are matched to all of the spreading codes and which obtain (a) a matched filter output signal y(x) for the x-th data bit b(x) and (b) matched filter output signals y(x+1) thru y(x+k-1) for the k-1 data bits that immediately follow data bit b(x); K is the number of bit sequences in the composite signal. An arithmetic unit combines the matched filter output signals via the expression: ##EQU1## where H(x,x±i) is the cross correlation of the spreading codes for data bits b(x) and b(x±i) over the time period that those data bits overlap (and thus add) in the composite signal, and ESTb(x-i) is an estimate of data bit b(x-i) which precedes bit b(x). An output unit decodes the data bit b(x) as a "1" if the above expression is positive, and as a "0" if the above expression is negative. In one embodiment, ESTb(x-i) is the SIGN of a matched filter output y(x-i) for data bit b(x-i). In another embodiment, ESTb(x-i) is the result from the output unit which decoded data bit b(x-i).
Inventors
- 👤 Robert T. Short
- 👤 Craig K. Rushforth
- 👤 Zhenhua Xie
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:36
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/69; H04B1/707
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
185 words
A circuit that decodes a data bit b(x) from a composite signal in which K asynchronous bit sequences, that are coded with respective spreading codes, are added together; said circuit being comprised of: filter means that are matched to all of said spreading codes and obtain (a) a matched filter output signals y(x) for said data bit b(x), (b) matched filter output signals y(x-1) thru y(x-K+1) for the K-1 data bits b(x-1) thru b(x-K+1) that immediately precede and partially overlap said data bit b(x) in said composite signal, and (c) matched filter output signals y(x+1) thru y(x+K-1) for the K-1 data bits b(x+1) thru b(x+K-1) that immediately follow and partially overlap said data bit b(x) in said composite signal; combining means for combining said matched filter output signals via the expression: ##EQU4## where H(x,x±i) is the cross correlation of said spreading codes for bits b(x) and b(x+i) over the time period that those bits are added in said composite signal; and, means for decoding said data bit b(x) as a "1" if said expression is positive, and as a "0" if said expression is negative.
Claim 2
Dependent Claim
185 words
A circuit that decodes a data bit b(x) from a composite signal in which K asynchronous bit sequences, that are coded with respective spreading codes, are added together; said circuit being comprised of: filter means that are matched to all of said spreading codes and obtain (a) a matched filter output signals y(x) for said data bit b(x), (b) matched filter output signals y(x-1) thru y(x-K+1) for the K-1 data bits b(x-1) thru b(x-K+1) that immediately precede and partially overlap said data bit b(x) in said composite signal, and (c) matched filter output signals y(x+1) thru y(x+K-1) for the K-1 data bits b(x+1) thru b(x+K-1) that immediately follow and partially overlap said data bit b(x) in said composite signal; combining means for combining said matched filter output signals via the expression: ##EQU4## where H(x,x±i) is the cross correlation of said spreading codes for bits b(x) and b(x+i) over the time period that those bits are added in said composite signal; and, means for decoding said data bit b(x) as a "1" if said expression is positive, and as a "0" if said expression is negative.
Claim 3
Dependent Claim
49 words
A circuit according to claim 1 and further including a control means for directing said combining means to increment the variable x in said expression by factors of K, 2K, 3K, . . . such that data bits in only one of said K asynchronous bit sequences are decoded.
Claim 4
Dependent Claim
69 words
A circuit according to claim 1 wherein said combining means includes a serial shift register having successive stages which shift from an input to an output, the terms of SIGN y(x+K-1) through SIGN y(x-K+1); and wherein an arithmetic means is coupled to said shift register, for sensing all of said shifted SIGN terms and in response combining all of said cross-correlations H(x,x±i) in parallel as specified by said expression.
Claim 5
Dependent Claim
28 words
A circuit according to claim 1 wherein said combining means is a specially programmed general purpose digital computer which combines said cross-correlations H(x,x±i) of said expression in series.
Claim 6
Dependent Claim
172 words
A circuit that decodes a data bit b(x) from a composite signal in which K asynchronous data bit sequences, that are coded with respective spreading codes, are added together; said circuit being comprised of: filter means that are matched to all of said spreading codes and obtain (a) a matched filter output signal y(x) for data bit b(x) and (b) matched filter output signals y(x+1 ) thru y(x+K-1) for the K-31 1 data bits b(x+1) thru b(x+K-i) that immediately follow and partially overlap data bit b(x) in said composite signal; combining means for combining said matched filter output signals via the expression: ##EQU5## where H(x,x+i) is the cross correlation of said spreading codes for data bits b(x) and b(x+i) over the time period that those data bits are added in said composite signal, and DEC b(x-i) is a decode of data bit b(x-i) which procedes bit b(x); and, means for decoding said data bit b(x) as a "1" if said expression is positive, and as a "0" if said expression is negative.
Claim 7
Dependent Claim
172 words
A circuit that decodes a data bit b(x) from a composite signal in which K asynchronous data bit sequences, that are coded with respective spreading codes, are added together; said circuit being comprised of: filter means that are matched to all of said spreading codes and obtain (a) a matched filter output signal y(x) for data bit b(x) and (b) matched filter output signals y(x+1 ) thru y(x+K-1) for the K-31 1 data bits b(x+1) thru b(x+K-i) that immediately follow and partially overlap data bit b(x) in said composite signal; combining means for combining said matched filter output signals via the expression: ##EQU5## where H(x,x+i) is the cross correlation of said spreading codes for data bits b(x) and b(x+i) over the time period that those data bits are added in said composite signal, and DEC b(x-i) is a decode of data bit b(x-i) which procedes bit b(x); and, means for decoding said data bit b(x) as a "1" if said expression is positive, and as a "0" if said expression is negative.
Claim 8
Dependent Claim
91 words
A circuit according to claim 5 wherein said combining means includes one serial shift register having successive stages which shift from an input to an output the terms of SIGN y(x+K-1) thru SIGN y(x-1) and another serial shift register having stages which shift from an input to an output the terms DEC b(x-1) thru DEC b(x-K+1); and wherein an arithmetic means is coupled to said shift registers for sensing said shifted SIGN and DEC terms and in response combining all of said cross-correlations H(x,x±i) in parallel as specified by said expression.
Claim 9
Dependent Claim
28 words
A circuit according to claim 5 wherein said combining means is a specially programmed general purpose digital computer which combines the cross-correlations H(x,x±i) of said expression in series.
Claim 10
Dependent Claim
170 words
A circuit that decodes a data bit b(x) from a composite signal in which K asynchronous data bit sequences, that are coded with respective spreading codes, are added together; said circuit being comprised of: filter means that are matched to all of said spreading codes and obtain (a) a matched filter output signal y(x) for data bit b(x) and (b) matched filter output signals y(x+1) thru y(x+K-1) for the K-1 data bits b(x+1) thru b(x+K-1) that immediately follow and partially overlap data bit b(x), in said composite signal; means for combining said matched filter output signals via the expression: ##EQU6## where H(x,x±i) is the cross correlation of said spreading codes for data bits b(x) and b(x±i) over the time period that those data bits are added in said composite signal, and EST b(x-i) is an estimate of data bit b(x-i) which precedes bit b(x); and, decoding means for decoding said data bit b(x) as a "1" if said expression is positive, and as a "0" if said expression is negative.
Claim 11
Dependent Claim
170 words
A circuit that decodes a data bit b(x) from a composite signal in which K asynchronous data bit sequences, that are coded with respective spreading codes, are added together; said circuit being comprised of: filter means that are matched to all of said spreading codes and obtain (a) a matched filter output signal y(x) for data bit b(x) and (b) matched filter output signals y(x+1) thru y(x+K-1) for the K-1 data bits b(x+1) thru b(x+K-1) that immediately follow and partially overlap data bit b(x), in said composite signal; means for combining said matched filter output signals via the expression: ##EQU6## where H(x,x±i) is the cross correlation of said spreading codes for data bits b(x) and b(x±i) over the time period that those data bits are added in said composite signal, and EST b(x-i) is an estimate of data bit b(x-i) which precedes bit b(x); and, decoding means for decoding said data bit b(x) as a "1" if said expression is positive, and as a "0" if said expression is negative.
Claim 12
Dependent Claim
26 words
A circuit according to claim 8 wherein EST b(x-i) is the SIGN of a matched filter output y(x-i) from said filter means for data bit b(x-i).
Claim 13
Dependent Claim
20 words
A circuit according to claim 8 wherein EST b(x-i) is a decode from said decoding means of data bit b(x-i).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-08 | 1995-01-07 | 1995-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-08 | 1999-01-07 | 1999-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-08 | 2003-01-07 | 2003-07-09 | $7700.00 | Window Closed / Lapsed |