Method and apparatus for decoding multiple bit sequences that are transmitted simultaneously in a single channel

Claim 3

A method according to claim 1 wherein each metric of said pair that is evaluated for bit b(x) includes an estimated value for bit b(x) times a matched filter output for bit b(x), minus an interference term I f which contains the matched filter outputs of the K-1 bits that immediately follow bit b(x), and minus an interference term I p which contains K-1 bits from the sequence b s , where K is the number of bit sequences in said composite signal.

Claim 4

A method according to claim 2 wherein said term I f is of the form ##EQU1## where y(i) is the matched filter output for bit b(i), and H(x,i) is the cross correlation between the spreading codes for bits b(x) and b(i) over the period that bits b(x) and b(i) overlap in said composite signal.

Claim 5

A method according to claim 3 wherein said term I p is of the form ##EQU2## where H(x,i) is the cross correlation between the spreading codes for bits b(x) and b(i) over the period that bits b(x) and b(i) overlap in said composite signal.

Claim 6

A method according to claim 4 wherein said metric for bit b(x) includes the terms 2b(x)y(x)-b 2 (x) W(x)-2b(x)I p (x)-2b(x)I f (x)-N o 1n2 where W(x) is the power level of bit b(x) and N o is the power level of any noise in the composite signal.

Claim 7

A method according to claim 5 wherein said composite signal is transmitted over said channel via radio waves.

Claim 8

A method according to claim 5 wherein said composite signal is transmitted over said channel via an electrical conductor.

Claim 9

A decoder for decoding superimposed data bits comprising: a plurality of filters, which are coupled to receive and filter a composite signal that is formed by coding multiple bit sequences with respective spreading codes and transmitting the coded bit sequences simultaneously and asynchronously over a single channel, with each filter being matched to a respective one of said spreading codes; a computing means for evaluating a metric for any bit b(x) in said composite signal which includes an estimated value for bit b(x), an estimate of a sequence of bits b s which immediately precede bit b(x), and matched filter outputs for several bits in said composite signal which immediately follow bit b(x); a plurality of register means, each of which is for holding a respective metric and a corresponding bit sequence; and a control means for repeatedly (a) examining said registers to determine its largest metric M max and corresponding bit sequence b s , (b) directing said computing means to compute a new pair of metrics for the bit sequences b s b(x)=0 and b s b(x)=1, and (c) replacing the register which contains said bit sequence b s with two registers, one of which contains the bit sequence b s b(x)=0 and the metric M max plus the above evaluated metric for b(x)=0, and the other of which contains the bit sequence b s b(x)=1 and the metric M max plus the above evaluated metric for b(x)=1.

Claim 10

A decoder for decoding superimposed data bits comprising: a plurality of filters, which are coupled to receive and filter a composite signal that is formed by coding multiple bit sequences with respective spreading codes and transmitting the coded bit sequences simultaneously and asynchronously over a single channel, with each filter being matched to a respective one of said spreading codes; a computing means for evaluating a metric for any bit b(x) in said composite signal which includes an estimated value for bit b(x), an estimate of a sequence of bits b s which immediately precede bit b(x), and matched filter outputs for several bits in said composite signal which immediately follow bit b(x); a plurality of register means, each of which is for holding a respective metric and a corresponding bit sequence; and a control means for repeatedly (a) examining said registers to determine its largest metric M max and corresponding bit sequence b s , (b) directing said computing means to compute a new pair of metrics for the bit sequences b s b(x)=0 and b s b(x)=1, and (c) replacing the register which contains said bit sequence b s with two registers, one of which contains the bit sequence b s b(x)=0 and the metric M max plus the above evaluated metric for b(x)=0, and the other of which contains the bit sequence b s b(x)=1 and the metric M max plus the above evaluated metric for b(x)=1.

Claim 11

A decoder according to claim 8 wherein said computing means evaluates a metric for bit b(x) which includes an estimated value for bit b(x) times a matched filter output for bit b(x), minus an interference term I f which contains the matched filter outputs of the K-1 bits that immediately follow bit b(x), and minus an interference term I p which contains K-1 bits from the sequence b s , where K is the number of bit sequences in said composite signal.

Claim 12

A decoder according to claim 9 wherein said terms I f and I p are of the form ##EQU3## and ##EQU4## where y(i) is the matched filter output for bit b(i), and H(x,i) is the cross correlation between the spreading codes for bits b(x) and b(i) over the period that bits b(x) and b(i) overlap in said composite signal.