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US5028552A
Expired / Lapsed
US
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Method of manufacturing insulated-gate type field effect transistor
Assignee: Toshiba Corp
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Filing: 1989-08-17
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Granted: 1991-07-02
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Expires: 2009-08-17
Abstract
Abstract A method of manufacturing an insulated-gate type field effect transistor includes the steps of forming an insulating film, on a semiconductor substrate, forming a polycrystalline silicon layer on the insulating film, forming a masking layer on the polycrystalline silicon layer, patterning the polycrystalline silicon and masking layers to form a gate electrode and a masking layer, doping an impurity of a first conductivity type in the semiconductor substrate using the gate electrode and the masking layer as masks, thereby forming a source region and a drain region, removing the masking layer, and ion-implanting an impurity of a second conductivity type in a region of the semiconductor substrate under the gate electrode through the gate electrode, thereby forming a channel-doped region. In this method, after the source and drain regions are formed, the impurity of the second conductivity type is ion-implanted in the substrate through the thin gate electrode to form the channel-doped region.
Inventors
- 👤 Yukihiro Ushiku
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:22
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D64/00; H10D64/01; H10D64/021; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/02; H10D84/03; H10D84/038; H10P; H10P30/00; H10P30/20; H10P30/22; Y; Y10; Y10S; Y10S148/00; Y10S148/082
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
252 words
A method of manufacturing an insulated-gate type field effect transistor, comprising the steps of: forming an insulating film, on a semiconductor substrate having a first semiconductor region of a second conductivity type; forming a polycrystalline silicon layer on said insulating film; forming a masking layer on said polycrystalline silicon layer; patterning said polycrystalline silicon layer and masking layer to form a first gate electrode and a first masking layer on that portion of the insulating film which is on the first semiconductor region, and a second gate electrode and a second masking layer on that portion of the insulating film which is on the second semiconductor region; forming a first resist layer on the second semiconductor region; doping an impurity of a second conductivity type in said first semiconductor region using said first gate electrode and said first masking layer as masks, thereby forming a first source region and a first drain region; removing the first resist layer; forming a second resist layer on the first semiconductor region; doping an impurity of a first conductivity type in said second semiconductor region using said second gate electrode and said second masking layer as masks, thereby forming a second source region and a second drain region; removing said second masking layer; and ion-implementing an impurity of a second conductivity type in a region of said second semiconductor region under said second gate electrode through said second gate electrode with said second resist layer remaining on said first semiconductor region, thereby forming a channel-doped region.
Claim 2
Independent Claim
252 words
A method of manufacturing an insulated-gate type field effect transistor, comprising the steps of: forming an insulating film, on a semiconductor substrate having a first semiconductor region of a second conductivity type; forming a polycrystalline silicon layer on said insulating film; forming a masking layer on said polycrystalline silicon layer; patterning said polycrystalline silicon layer and masking layer to form a first gate electrode and a first masking layer on that portion of the insulating film which is on the first semiconductor region, and a second gate electrode and a second masking layer on that portion of the insulating film which is on the second semiconductor region; forming a first resist layer on the second semiconductor region; doping an impurity of a second conductivity type in said first semiconductor region using said first gate electrode and said first masking layer as masks, thereby forming a first source region and a first drain region; removing the first resist layer; forming a second resist layer on the first semiconductor region; doping an impurity of a first conductivity type in said second semiconductor region using said second gate electrode and said second masking layer as masks, thereby forming a second source region and a second drain region; removing said second masking layer; and ion-implementing an impurity of a second conductivity type in a region of said second semiconductor region under said second gate electrode through said second gate electrode with said second resist layer remaining on said first semiconductor region, thereby forming a channel-doped region.
Claim 3
Dependent Claim
16 words
A method according to claim 1 wherein said insulating material is silicon oxide or silicon nitride.
Claim 4
Dependent Claim
16 words
A method according to claim 1 wherein said insulating material is silicon oxide or silicon nitride.
Claim 5
Dependent Claim
21 words
A method according to claim 1 wherein a thickness of said first and second gate electrode is 500 to 2500 Å.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1994-07-01 | 1994-12-31 | 1995-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-01 | 1998-12-31 | 1999-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-01 | 2002-12-31 | 2003-07-02 | $7700.00 | Window Closed / Lapsed |