US5027322A
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Circuit configuration for identification of integrated semiconductor circuitries
Assignee: Qimonda AG
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Filing: 1990-06-29
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Granted: 1991-06-25
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Expires: 2010-06-29
Abstract
Abstract A circuit configuration for the identification of integrated semiconductor circuitries includes n programmable elements. A common line is connected to the programmable elements. An n-stage serial-parallel shift register has a data input, n parallel outputs, and a clock input for controlling a shift function of the serial-parallel shift register as a function of a clock signal to be applied to the clock input. Transistors each have a drain connected to a respective one of the programmable elements, a source connected to a supply potential, and a gate connected to a respective one of the parallel outputs of the serial-parallel shift register. Instead of n-stage serial-parallel shift register, it is also possible to use a clocked n-stage oscillator, such as a ring oscillator, or an n-stage counter, such as ring counter.
Inventors
- 👤 Wolfgang Pribyl
- 👤 Raymond Sittig
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 01:10
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/201; H10P; H10P74/00; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/493; H10W46/00; H10W46/401; H10W46/403; H10W46/601
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
100 words
Circuit configuration for the identification of integrated semiconductor circuitries, comprising: n programmable elements, a common line connected to said programmable elements, an n-stage serial-parallel shift register having a data input, n parallel outputs, and a clock input for controlling a shift function of said serial-parallel shift register as a function of a clock signal to be applied to the clock input, and transistors each having a drain connected to a respective one of said programmable elements, a source connected to a supply potential, and a gate connected to a respective one of the parallel outputs of said serial-parallel shift register.
Claim 2
Dependent Claim
100 words
Circuit configuration for the identification of integrated semiconductor circuitries, comprising: n programmable elements, a common line connected to said programmable elements, an n-stage serial-parallel shift register having a data input, n parallel outputs, and a clock input for controlling a shift function of said serial-parallel shift register as a function of a clock signal to be applied to the clock input, and transistors each having a drain connected to a respective one of said programmable elements, a source connected to a supply potential, and a gate connected to a respective one of the parallel outputs of said serial-parallel shift register.
Claim 3
Dependent Claim
14 words
Circuit configuration according to claim 1, wherein said programmable elements are mechanically disconnectable means.
Claim 4
Dependent Claim
14 words
Circuit configuration according to claim 1, wherein said programmable elements are thermally disconnectable means.
Claim 5
Dependent Claim
14 words
Circuit configuration according to claim 1, wherein said programmable elements are chemically disconnectable means.
Claim 6
Dependent Claim
18 words
Circuit configuration according to claim 1, wherein said programmable elements are disconnectable means in the form of resistors.
Claim 7
Dependent Claim
14 words
Circuit configuration according to claim 5, wherein said resistors are transistors connected as resistors.
Claim 8
Dependent Claim
13 words
Circuit configuration according to claim 1, wherein said programmable elements are laser fuses.
Claim 9
Dependent Claim
14 words
Circuit configuration according to claim 1, wherein said programmable elements are disconnectable conductor tracks.
Claim 10
Dependent Claim
20 words
Circuit configuration according to claim 1, including means for connecting said common line to another supply potential with high impedance.
Claim 11
Dependent Claim
95 words
Circuit configuration for the identification of integrated semiconductor circuitries, comprising: n programmable elements, a common line connected to said programmable elements, a clocked n-stage oscillator having a data input, n parallel outputs, and a clock input for controlling a start function of said oscillator as a function of a clock signal to be applied to the clock input, and transistors each having a drain connected to a respective one of said programmable elements, a source connected to a supply potential, and a gate connected to a respective one of the parallel outputs of said oscillator.
Claim 12
Dependent Claim
95 words
Circuit configuration for the identification of integrated semiconductor circuitries, comprising: n programmable elements, a common line connected to said programmable elements, a clocked n-stage oscillator having a data input, n parallel outputs, and a clock input for controlling a start function of said oscillator as a function of a clock signal to be applied to the clock input, and transistors each having a drain connected to a respective one of said programmable elements, a source connected to a supply potential, and a gate connected to a respective one of the parallel outputs of said oscillator.
Claim 13
Dependent Claim
13 words
Circuit configuration according to claim 10, wherein said oscillator is a ring oscillator.
Claim 14
Dependent Claim
94 words
Circuit configuration for the identification of integrated semiconductor circuitries, comprising: n programmable elements, a common line connected to said programmable elements, an n-stage counter having a data input, n parallel outputs, and a clock input for controlling a counting function of said counter as a function of a clock signal to be applied to the clock input, and transistors each having a drain connected to a respective one of said programmable elements, a source connected to a supply potential, and a gate connected to a respective one of the parallel outputs of said counter.
Claim 15
Dependent Claim
94 words
Circuit configuration for the identification of integrated semiconductor circuitries, comprising: n programmable elements, a common line connected to said programmable elements, an n-stage counter having a data input, n parallel outputs, and a clock input for controlling a counting function of said counter as a function of a clock signal to be applied to the clock input, and transistors each having a drain connected to a respective one of said programmable elements, a source connected to a supply potential, and a gate connected to a respective one of the parallel outputs of said counter.
Claim 16
Dependent Claim
13 words
Circuit configuration according to claim 12, wherein said counter is a ring counter.
Claim 17
Dependent Claim
92 words
Circuit configuration for the identification of integrated semiconductor circuitries, comprising: n programmable elements, a common line connected to said programmable elements, means having a data input, n parallel outputs, and a clock input for consecutively activating the parallel outputs as a function of a clock signal to be applied to the clock input, and transistors each having a drain connected to a respective one of said programmable elements, a source connected to a supply potential, and a gate connected to a respective one of the parallel outputs of said serial-parallel shift register.
Claim 18
Dependent Claim
92 words
Circuit configuration for the identification of integrated semiconductor circuitries, comprising: n programmable elements, a common line connected to said programmable elements, means having a data input, n parallel outputs, and a clock input for consecutively activating the parallel outputs as a function of a clock signal to be applied to the clock input, and transistors each having a drain connected to a respective one of said programmable elements, a source connected to a supply potential, and a gate connected to a respective one of the parallel outputs of said serial-parallel shift register.
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