Circuit configuration for protecting an electronic circuit against overload

Claim 2

Circuit configuration for protecting electronic circuits against overload of a supply voltage source, comprising a voltage-limiting configuration, and a depletion layer field effect transistor having a drain terminal and interconnected gate and source terminals, said drain terminal being connected to said voltage limiting configuration and said interconnected gate and source terminal being connected to the supply voltage source.

Claim 3

Circuit configuration according to claim 1, wherein said voltage-limiting configuration is a Zener diode.

Claim 4

Circuit configuration according to claim 1, wherein said depletion layer field effect transistor is split into first and second subtransistors of the same conductivity type having gate, source and drain terminals, the gate and source terminals of said second subtransistor being connected to the gate terminal of said first subtransistor, and the drain terminals of said first and second subtransistors being interconnected.

Claim 5

Circuit configuration according to claim 1, including at least one additional depletion layer field effect transistor, said additional depletion layer field effect transistor being connected in series with said depletion layer field effect transistor.

Claim 6

Circuit configuration according to claim 1, including an MOS field effect transistor having a drain terminal connected to ground and gate and source terminals connected to the supply voltage source.

Claim 7

Circuit configuration according to claim 5, including a semiconductor layer of a first conductivity type having a well of a second conductivity type formed therein and having a surface, said depletion layer field effect transistor being split into first and second subtransistors integrated into said semiconductor layer along with said MOS field effect transistor, a centrally disposed structure and two striated structures of the second conductivity type being more strongly doped than said well and being disposed in said well, striated structures of the first conductivity type being more strongly doped than said semiconductor layer and each of said striated structures of the first conductivity type being disposed between one of said striated structures of the second conductivity type and said centrally disposed structure, an insulation layer on said surface having recesses formed therein above said centrally disposed structure and said striated structures of the second conductivity type, and a metallization layer of said insulation layer corresponding to the course of said striated structures of the second conductivity type and said centrally disposed structure, said metallization layer extending into said recesses in said insulation layer as far as said centrally disposed structures and said striated structures of the second conductivity type, and having an outermost ring extending past said well and past said semiconductor.

Claim 8

Circuit configuration according to claim 6, wherein said first and second subtransistors are of the same conductivity type and have gate, source and drain terminals, the gate and source terminals of said second subtransistor being connected to the gate terminal of said first subtransistor, and the drain terminals of said first and second subtransistors being interconnected.

Claim 9

Circuit configuration according to claim 6, wherein the circuit configuration is jointly integrated with the circuit to be protected.