Input protective circuit device

Abstract

Abstract PURPOSE:To ensure operation even when high integration is contrived by a method wherein an input protective circuit for C-MOS is composed by utilizing an element with a low voltage. CONSTITUTION:A pair of P type well regions 2 and 2' are penetrated in an N type Si substrate 1 in the depth direction and formed by splitting in the right and left directions through a vacant section having sufficiently narrow width, and an N<+> type region 3 is formed by diffusion at the circumference of opposing well regions 2 and 2', extending over the vacant section 6. Next, thick SiO2 films 5 are deposited on the whole surface, the end sections on the regions 3, 2 and 2' are removed, and P<+> type regions 4 and 4' are formed by diffusion in the exposed regions 2 and 2' respectively. In this way composition, input is connected to the region 3 through a resistor and the regions 2 and 2' are connected to a low electrical potential through the regions 4 and 4' and the substrate 1 is connected to a high electrical potential. In this way, a J-FET is produced by composing junction-type diodes between the regions 3 and 2, and 3 and 2', the region 2 as a drain the substrate 1 as a source and regions 2 and 2' as gates and these are connected in parallel.

Inventors

• 👤 Noburo Tanimura

Bibliographic Details