Patent US5027005A successfully refreshed from Google Patents.
US5027005A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic circuit which can be selected to function as a d or t type flip-flop
Assignee: Fujitsu VLSI Ltd
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Filing: 1990-01-18
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Granted: 1991-06-25
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Expires: 2010-01-18
Abstract
Abstract A logic circuit comprises a first terminal for receiving an input data signal, a second terminal for receiving a clock signal, a first latch circuit coupled to the first and second terminals for latching the input data signal responsive to the clock signal, a second latch circuit coupled to the first latch circuit for latching an output signal of the first latch circuit, a third terminal for outputting an output data signal which is output from the second latch circuit, and a selecting part coupled to the third terminal for selectively feeding back the output data signal to the first latch circuit in a first mode and for cutting off the feedback of the output data signal to the first latch circuit in a second mode, where the logic circuit operates as a toggle flip-flop in the first mode and operates as a delay flip-flop in the second mode. The input data signal received by the first terminal selectively identifies one of the two modes of the flip-flop.
Inventors
- 👤 Tatsuaki Kitsuta
- 👤 Isao Shimotsuhama
- 👤 Yoshio Watanabe
- 👤 Masahiro Tanaka
- 👤 Shinichi Shiotsu
- 👤 Kazumi Ogawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:13
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K3/2885; H03K19/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
175 words
A logic circuit having first and second modes, and comprising: first terminal means for receiving an open-circuited signal which designates the first mode and an input data signal which designates the second mode; second terminal means for receiving a clock signal; first latch means coupled to said first and said second terminal means for latching and for providing as a first output signal in response to the clock signal, the input data signal; second latch means coupled to said first latch means for latching, and for providing as a second output signal, the first output signal; third terminal means for outputting the second output signal; and selecting means, coupled to said third terminal means, for selectively feeding back the second output signal to said first latch means responsive to said first terminal means receiving one of the open-circuited signal and the input data signal such that the logic circuit functions as a toggle flip-flop in the first mode and functions as a delay flip-flop in the second mode, without requiring a change in physical wiring.
Claim 2
Dependent Claim
175 words
A logic circuit having first and second modes, and comprising: first terminal means for receiving an open-circuited signal which designates the first mode and an input data signal which designates the second mode; second terminal means for receiving a clock signal; first latch means coupled to said first and said second terminal means for latching and for providing as a first output signal in response to the clock signal, the input data signal; second latch means coupled to said first latch means for latching, and for providing as a second output signal, the first output signal; third terminal means for outputting the second output signal; and selecting means, coupled to said third terminal means, for selectively feeding back the second output signal to said first latch means responsive to said first terminal means receiving one of the open-circuited signal and the input data signal such that the logic circuit functions as a toggle flip-flop in the first mode and functions as a delay flip-flop in the second mode, without requiring a change in physical wiring.
Claim 3
Dependent Claim
58 words
The logic circuit as claimed in claim 1, wherein said selecting means comprises feed-back means for feeding back the second output signal to said first latch means when said first terminal means receives the open-circuited signal and for blocking the second output signal from said first latch means when said first terminal means receives the input data signal.
Claim 4
Dependent Claim
67 words
The logic circuit as claimed in claim 2, wherein said first latch means includes means for receiving the input data signal having first and second voltage levels, and wherein said second latch means includes means for outputting the second output data signal having a third voltage level set between said first and second voltage levels, and a fourth voltage level set lower than said second voltage level.
Claim 5
Dependent Claim
40 words
The logic circuit as claimed in claim 2, further comprising: test means for blocking said first terminal means from receiving the input data signal, and for permitting said second terminal means to receive the clock signal in said first mode.
Claim 6
Dependent Claim
78 words
The logic circuit as claimed in claim 1, wherein said first latch means includes means for receiving a first select signal having a first and second logic level, and wherein said selecting means comprises feed-back means for feeding back the second output signal to said first latch means when the select signal has the first logic level and for blocking the second output signal from said first latch means when the select signal has the second logic level.
Claim 7
Dependent Claim
190 words
The logic circuit as claimed in claim 5 wherein said selecting means comprises a first data input part which comprises first, second and third transistors, a second data input part which comprises fourth, fifth and sixth transistors, and a selection signal control part, said first and second transistors having emitters which are connected in common and bases which are coupled to said output terminal means, said third transistor having a collector which is connected to the emitters of said first and second transistors, said fourth and fifth transistors having emitters which are connected in common, at least one of said fourth and fifth transistors having a base which is coupled to said first terminal means, said sixth transistor having a collector which is connected to the emitters of said fourth and fifth transistors and an emitter which is connected to the emitter of said third transistor, said selection signal control part outputs a selection signal which is supplied to a base of at least one of said third and sixth transistors in response to the select signal, so that one of said first and second data input parts is operated.
Claim 8
Dependent Claim
60 words
The logic circuit as claimed in claim 6, further comprising: means for receiving the clock signal having first and second voltage levels, and wherein said selecting means includes means for receiving a second select signal having a third voltage level set between said first and second voltage levels, and a fourth voltage level set lower than said second voltage level.
Claim 9
Dependent Claim
40 words
The logic circuit as claimed in claim 5, further comprising: test means for blocking said first terminal means from receiving the input data signal, and for permitting said second terminal means to receive the clock signal in said first mode.
Claim 10
Dependent Claim
144 words
A logic circuit having first and second modes, and comprising: first terminal means for receiving an open-circuited signal which designates the first mode and an input data signal which designates the second mode; second terminal means for receiving a clock signal; first latch means coupled to said first and said second terminal means for latching, and for providing as a first output signal in response to the clock signal, the input data signal; second latch means coupled to said first latch means for latching, and for providing as a second output signal, the first output signal; third terminal means for outputting the second output signal; and selecting means, coupled to said third terminal means, for selectively feeding back the second output signal to said first latch means responsive to said first terminal means receiving one of the open-circuited signal and the input data signal.
Claim 11
Dependent Claim
144 words
A logic circuit having first and second modes, and comprising: first terminal means for receiving an open-circuited signal which designates the first mode and an input data signal which designates the second mode; second terminal means for receiving a clock signal; first latch means coupled to said first and said second terminal means for latching, and for providing as a first output signal in response to the clock signal, the input data signal; second latch means coupled to said first latch means for latching, and for providing as a second output signal, the first output signal; third terminal means for outputting the second output signal; and selecting means, coupled to said third terminal means, for selectively feeding back the second output signal to said first latch means responsive to said first terminal means receiving one of the open-circuited signal and the input data signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-24 | 1994-12-24 | 1995-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-24 | 1998-12-24 | 1999-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-24 | 2002-12-24 | 2003-06-25 | $7700.00 | Window Closed / Lapsed |