Combined data and set-reset flip-flop with provisions for eliminating race conditions

Claim 2

A bistable circuit, comprising a reset input terminal, an information input terminal, a command input terminal, an output terminal, a first AND-gate, an OR-gate, means for cross-coupling the first AND-gate and the OR-gate thereby forming a feedback loop, means connecting the reset terminal to an input of the first AND-gate, a second AND-gate, means connecting the information terminal to an input of the second AND-gate, means connecting the output of the second AND-gate to an input of the OR-gate, means coNnecting the output terminal of the bistable circuit to the feedback loop, means connecting the command signal to an input of both the first and second AND-gates thereby forming a signal path between the command input terminal and the input of the OR-gate, and an invertor connected in the signal path between the command input terminal and the OR-gate.

Claim 3

A circuit as claimed in claim 1, wherein the means for cross-coupling the first AND-gate and the OR-gate comprises a third AND-gate having an input connected to an output of the OR-gate and having an output connected to an input of the first AND-gate, and wherein the means connecting the control input terminal to input terminals of the first and second AND-gates comprises means connecting the control input terminal to an input terminal of the third AND-gate.

Claim 4

A bistable circuit as claimed in claim 2, wherein the means connecting the control input terminal to an input terminal of the third AND-gate comprises a second OR-gate means connecting an input the second OR-gate to the control input terminal, and means connecting an output of the second OR-gate to an input of the third AND-gate, the bistable circuit further comprising means connecting the information input terminal to an input terminal of the second OR-gate.

Claim 5

Apparatus as claimed in claim 3, wherein the means connecting the control input terminal to an input terminal of the second OR-gate comprises a fourth AND-gate, means connecting the control input terminal to an input of the fourth AND-gate, and means connecting an output of the fourth AND-gate to an input of the second OR-gate.

Claim 6

A bistable circuit as claimed in claim 4, wherein the means connecting the control input terminal to inputs of the first and second AND-gates comprises means connecting an output of the fourth AND-gate to an input of the second AND-gate.

Claim 7

A bistable circuit as claimed in claim 5, wherein the means connecting the information input terminal to an input of the second OR-gate comprises a fifth AND-gate, means connecting the information input terminal to an input of the fifth AND-gate, and means connecting an output of the fifth AND-gate to an input of the second OR-gate.

Claim 8

Apparatus as claimed in claim 2, wherein the third AND-gate comprises a wired AND-gate.

Claim 9

Apparatus as claimed in claim 3, wherein the first and second OR-gates each comprise a wired OR-gate.

Claim 10

A bistable circuit, comprising a reset input terminal, an information terminal, a control input terminal, a first AND-gate having an input connected to the reset input terminal, a first OR-gate, means connecting the output of the first AND-gate to an input of the first OR-gate, a second AND-gate, means connecting an output of the first OR-gate to an input of the second AND-gate, means connecting an output of the second AND-gate to an input of the first AND-gate, the first and second AND-gates and the first OR-gate thereby forming a feedback loop, an output terminal connected to an output of the second AND-gate, a third AND-gate, means connecting an output of the third AND-gate to an input of the first OR-gate, means connecting the information input terminal to an input of the third AND-gate, invertor means connecting the control input terminal to an input terminal of the third AND-gate, a second OR-gate, means connecting separate inputs of the second OR-gate to the information input terminal and to the control input terminal, and means connecting the output of the second OR-gate to an input of the second AND-gate.

Claim 11

A bistable circuit, comprising a reset input terminal, an information terminal, a control input terminal, a first AND-gate having an input connected to the reset input terminal, a first OR-gate, means connecting the output of the first AND-gate to an input of the first OR-gate, a second AND-gate, means connecting an output of the first OR-gate to an input of the second AND-gate, means connecting an output of the second AND-gate to an input of the first AND-gate, the first and second AND-gates and the first OR-gate thereby forming a feedback loop, an output terminal connected to an output of the second AND-gate, a third AND-gate, means connecting an output of the third AND-gate to an input of the first OR-gate, means connecting the information input terminal to an input of the third AND-gate, invertor means connecting the control input terminal to an input terminal of the third AND-gate, a second OR-gate, means connecting separate inputs of the second OR-gate to the information input terminal and to the control input terminal, and means connecting the output of the second OR-gate to an input of the second AND-gate.