Asynchronous rs sweep stage in ecl technique

Claim 1

An asynchronous emitter-coupled sweep stage comprising a first emitter-coupled current switch including first and second transistors, and a third transistor, first, second and third resistances, a diode, a fourth transistor, and a second emittercoupled current switch including fifth, sixth and seventh transistors, an eighth transistor, all of said transistors including a base, an emitter and a collector, the base of said first transistor adapted to receive a reset signal, the base of said second transistor connected to a first reference potential, the emitters of said first and second transistors coupled to a second reference potential, said third transistor forming an emitter follower and having its base connected to the collector of said second transistor and jointly therewith by way of said first resistance to a third reference potential, the emitter of said third transistor for providing an inverted form of the output signal, said fourth transistor forming an emitter follower with its collector connected to said third reference potential and its base connected to the collectors of said first and fifth transistors and by way of said second resistance and said diode in parallel to the third reference potential, the emitter of said fourth transistor for providing the output signal and connected to the base of said sixth transistor, the emitters of said fifth, sixth and seventh transistors connected to the second reference potential and the collectors of said sixth and seventh transistors connected to the base of the eighth transistor and by way of said third resistance to the third reference potential, the emitters and collectors of said third and eighth transistors being respectively connected and said collectors connected to said third reference potential, the base of said seventh transistor adapted to receive a set signal and the base of said fifth transistor connected to the first reference potential whereby the inputs to the bases of said third and eighth transistors from a wired OR function to effect provision of the inverted output signal.