US4525641A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Flip-flop programmer using cascaded logic arrays
Assignee: International Business Machines Corp
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Filing: 1982-12-10
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Granted: 1985-06-25
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Expires: 2002-12-10
Abstract
Abstract Cascaded programmable logic arrays are used to program any type of flip-flop. The latch itself can be embedded in the array when using cascaded PLA's. The arrays can be cascaded to provide logic functions using less total area than a single array embodying the same function.
Inventors
- 👤 Claude A. Cruz
- 👤 Johannes C. Vermeulen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 19:24
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
118 words
A circuit for implementing any given flip-flop circuit comprising, in combination: flip-flop means of at least one type having input means and output means; first and second logic array means having input means and output means for supplying as signals at their output means selective logic derivations of signals applied to their input means; means for coupling said output means of said second array means to the input means of said flip-flop means; means for coupling said output means of said flip-flop means to said input means of the first and second logic array means; and means for coupling said output means of said first logic array means to the input means of said second logic array means.
Claim 2
Dependent Claim
118 words
A circuit for implementing any given flip-flop circuit comprising, in combination: flip-flop means of at least one type having input means and output means; first and second logic array means having input means and output means for supplying as signals at their output means selective logic derivations of signals applied to their input means; means for coupling said output means of said second array means to the input means of said flip-flop means; means for coupling said output means of said flip-flop means to said input means of the first and second logic array means; and means for coupling said output means of said first logic array means to the input means of said second logic array means.
Claim 3
Dependent Claim
180 words
A logic system comprising: a plurality of flip-flop means having input means and output means and clock signal receiving means for supplying at said output means sequential count values in response to active signals at said clock signal receiving means; first programmable logic array means comprising OR-array means arranged to receive input signals and AND-array means arranged to supply output signals; second programmable logic array means comprising AND-array means arranged to receive input signals and OR-array means arranged to supply output signals; means for coupling said output means of said plurality of flip-flop means as input signals to said first programmable logic array means; means for coupling said output means of said plurality of flip-flop means as subset of said input signals to said second programmable logic array means; means for coupling said output signals from said first programmable logic array means as a disjoint subset of input signals to said second programmable logic array means; and means for coupling said output signals from said second programmable logic array means to said input means of said plurality of flip-flop means.
Claim 4
Dependent Claim
180 words
A logic system comprising: a plurality of flip-flop means having input means and output means and clock signal receiving means for supplying at said output means sequential count values in response to active signals at said clock signal receiving means; first programmable logic array means comprising OR-array means arranged to receive input signals and AND-array means arranged to supply output signals; second programmable logic array means comprising AND-array means arranged to receive input signals and OR-array means arranged to supply output signals; means for coupling said output means of said plurality of flip-flop means as input signals to said first programmable logic array means; means for coupling said output means of said plurality of flip-flop means as subset of said input signals to said second programmable logic array means; means for coupling said output signals from said first programmable logic array means as a disjoint subset of input signals to said second programmable logic array means; and means for coupling said output signals from said second programmable logic array means to said input means of said plurality of flip-flop means.
Claim 5
Dependent Claim
28 words
The invention as claimed in claim 2 further comprising: means for coupling a control signal as one of the input signals to said first programmable logic array means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-06-24 | 1988-12-24 | 1989-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-06-24 | 1992-12-24 | 1993-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-06-24 | 1996-12-24 | 1997-06-25 | $7700.00 | Window Closed / Lapsed |