Patent US5026666A successfully refreshed from Google Patents.
US5026666A
Expired / Lapsed
US
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Method of making integrated circuits having a planarized dielectric
Assignee: Nokia Bell Labs
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Filing: 1989-12-28
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Granted: 1991-06-25
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Expires: 2009-12-28
Abstract
Abstract An integrated circuit is made by a technique that provides a planar dielectric over gate, source, and drain regions without over-etching of the gate contact region, In the inventive process, the contact windows are etched in the conformal dielectric prior to the planarization step, so that the etch thickness is the same for the gate as for the source/drain windows. Then, a sacrificial planarizing polymer (e.g., a photoresist) is deposited to cover the conformal dielectric and fill the etched windows. Finally, a planarizing etch-back is performed, and the polymer is removed from the contact windows. A planarized dielectric is achieved without excessive etching of the gate windows.
Inventors
- 👤 Graham W. Hills
- 👤 Robert D. Huttemann
- 👤 Kolawole R. Olasupo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:37
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10W20/081; Y; Y10; Y10S; Y10S438/00; Y10S438/959
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
112 words
A method of making an integrated circuit in a semiconductor body by steps comprising: forming a gate region that includes a gate dielectric overlying said body, and a gate conductor overlying said gate dielectric; and forming source and drain doped regions in said semiconductor body, characterized by the further steps of: forming a dielectric layer so as to have an approximately equal thickness on gate, source and drain contact regions; etching contact windows into said dielectric layer; planarizing said dielectric layer after said etching; and forming electrically conductive material in said windows after said planarizing so as to form electrical contacts to said gate, source, and drain contact regions through said windows.
Claim 2
Independent Claim
112 words
A method of making an integrated circuit in a semiconductor body by steps comprising: forming a gate region that includes a gate dielectric overlying said body, and a gate conductor overlying said gate dielectric; and forming source and drain doped regions in said semiconductor body, characterized by the further steps of: forming a dielectric layer so as to have an approximately equal thickness on gate, source and drain contact regions; etching contact windows into said dielectric layer; planarizing said dielectric layer after said etching; and forming electrically conductive material in said windows after said planarizing so as to form electrical contacts to said gate, source, and drain contact regions through said windows.
Claim 3
Dependent Claim
13 words
The method of claim 1 wherein said gate conductor includes a metal silicide.
Claim 4
Dependent Claim
19 words
The method of claim 2 wherein said source and drain doped regions have a metal silicide layer formed thereon.
Claim 5
Dependent Claim
12 words
The method of claim 2 wherein said metal silicide is titanium silicide.
Claim 6
Dependent Claim
59 words
The method of claim 1 wherein said planarizing is accomplished by steps comprising depositing a sacrificial planarizing material so as t cover said dielectric layer and at least partially fill said windows, thereby obtaining a relatively flat surface of said material, and etching said sacrificial planarizing material so as to transfer its relatively flat surface into said dielectric layer.
Claim 7
Dependent Claim
15 words
The method of claim 1 wherein said planarizing is accomplished by polishing said dielectric layer.
Claim 8
Dependent Claim
21 words
The method of claim 1 wherein said forming electrically conductive material includes the step of forming conductive plugs in said windows.
Claim 9
Dependent Claim
22 words
The method of claim 7 further comprising the step of forming a conductive interconnect pattern that contacts said plugs in said windows.
Claim 10
Dependent Claim
12 words
The method of claim 1 wherein said dielectric layer is silicon dioxide.
Claim 11
Dependent Claim
14 words
The method of claim 1 wherein said dielectric layer is formed by conformal deposition.
Claim 12
Dependent Claim
19 words
The method of claim 10 wherein said dielectric layer is silicon dioxide deposited by decomposition of tetraethoxysilane (TEOS) gas.
Claim 13
Dependent Claim
35 words
The method of claim 1 wherein said dielectric layer is formed by directional deposition so that the thickness of said dielectric layer is greater on horizontal surfaces than on vertical surfaces of said integrated circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-24 | 1994-12-24 | 1995-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-24 | 1998-12-24 | 1999-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-24 | 2002-12-24 | 2003-06-25 | $7700.00 | Window Closed / Lapsed |