Patent US5025210A successfully refreshed from Google Patents.
US5025210A
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Evaluation facilitating circuit device
Assignee: Toshiba Corp
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Filing: 1988-10-11
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Granted: 1991-06-18
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Expires: 2008-10-11
Abstract
Abstract An evaluation facilitating circuit is for selectively evaluating each of block of a logical circuit to be checked which is divided into the plurality of blocks. The evaluation facilitating circuit includes a data hold circuit for selectively latching level signals of nodes of each of blocks and a data hold and transfer control circuit for controlling the data hold circuit.
Inventors
- 👤 Toshiyuki Yaguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:28
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318505
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
162 words
An evaluation facilitating circuit for evaluating a logical circuit which is divided into a plurality of blocks, comprising: (a) latch means for latching level signals at each of the nodes in one of said blocks of said logical circuit, said latch means comprising a plurality of latch circuits arranged in a matrix array and a data hold and transfer control circuit for controlling the latch operation of each of said latch circuits and a transfer operation in which latched level signals are transferred externally, latched data in said latch means reflecting an instant condition of said nodes in one block; and (b) a selection circuit for selecting level signals of nodes of one block of said blocks from the level signals of nodes of the other blocks of said blocks and for supplying said selected level signals of said one block to said latch means in order to represent a condition of said one block by a condition of said latch means.
Claim 2
Dependent Claim
162 words
An evaluation facilitating circuit for evaluating a logical circuit which is divided into a plurality of blocks, comprising: (a) latch means for latching level signals at each of the nodes in one of said blocks of said logical circuit, said latch means comprising a plurality of latch circuits arranged in a matrix array and a data hold and transfer control circuit for controlling the latch operation of each of said latch circuits and a transfer operation in which latched level signals are transferred externally, latched data in said latch means reflecting an instant condition of said nodes in one block; and (b) a selection circuit for selecting level signals of nodes of one block of said blocks from the level signals of nodes of the other blocks of said blocks and for supplying said selected level signals of said one block to said latch means in order to represent a condition of said one block by a condition of said latch means.
Claim 3
Dependent Claim
32 words
The evaluation facilitating circuit as claimed in claim 1, wherein said selection circuit is constructed for receiving the level signals of nodes of said plurality of said all blocks through data lines.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-17 | 1994-12-17 | 1995-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-17 | 1998-12-17 | 1999-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-17 | 2002-12-17 | 2003-06-18 | $7700.00 | Window Closed / Lapsed |