EP0077237A1
Expired / Lapsed
EP
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Digital tester local memory data storage system
Assignee: Fairchild Semiconductor Corp
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Filing: 1982-09-28
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Granted: —
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Expires: 2002-09-28
Abstract
Abstract In a digital tester for evaluating electronic components, a local memory unit for each data channel in the tester is loaded with test vector information only in the locations of the memory relating to transitions that take place in the operation of the data channel. In addition, a transition bit is stored in each memory location to signify whether the vector information in that location represents valid transition data. The transition bit is used to control the reading of information from the memory into a register that controls the flow of information in the data channel, so that only the valid transition vectors are fed into data channel control circuitry. This procedure substantially reduces the amount of data that must be loaded into the memory, and hence reduces the total time necessary to thoroughly test a circuit.
Inventors
- 👤 Maurice E. Carey
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 00:40
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31919; G01R31/31921; G06; G06F; G06F9/00
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
131 words
A method of operating a digital tester for testing electronic components, said tester having a data channel that is operatively connected to the electronic component including an associated local memory which stores digital information relating to the operation to be performed in the data channel during a test and is addressed during each cycle in the testing procedure, characterized by the steps of: storing vectors describing transitions to be made in the operation to be performed in the data channel only at the address locations of the local memory that correspond to the test cycles in which said transitions are to take place; and storing into each address location of said local memory data that is indicative of whether the vector information stored in said address location is valid transition data.
Claim 2
Independent Claim
131 words
A method of operating a digital tester for testing electronic components, said tester having a data channel that is operatively connected to the electronic component including an associated local memory which stores digital information relating to the operation to be performed in the data channel during a test and is addressed during each cycle in the testing procedure, characterized by the steps of: storing vectors describing transitions to be made in the operation to be performed in the data channel only at the address locations of the local memory that correspond to the test cycles in which said transitions are to take place; and storing into each address location of said local memory data that is indicative of whether the vector information stored in said address location is valid transition data.
Claim 3
Dependent Claim
14 words
The method of claim 1 characterized in that said data is a single bit.
Claim 4
Dependent Claim
74 words
The method of claim 1 or 2 characterized by the steps of: addressing a location in said local memory during each cycle of the testing procedure; feeding the information stored in the addressed location of said local memory to a data channel control circuit; and enabling said data channel control circuit to receive the information only from those address locations in which said stored control bit indicates that a valid transition vector is stored.
Claim 5
Dependent Claim
62 words
The method of claim 3 characterized in that said data channel control circuit includes a register and said control bit controls a clock signal to said register so that the register is triggered by the clock signal to receive information from said local memory only when the control bit indicates a memory location containing a valid transition vector is presently being addressed.
Claim 6
Dependent Claim
56 words
The method of claim 1 or 2 characterized by the steps of: reading one of said stored control bits during each cycle of the test procedure; and feeding a stored test vector to a data channel control circuit only during those test cycles in which the control bit indicates that a transition is to take place.
Claim 7
Dependent Claim
68 words
The method of claim 1 or 2 characterized by the steps of: addressing a location in the local memory during each cycle of the testing procedure; accessing the information stored in the addressed location of the local memory; and inhibiting a data channel control circuit from receiving the accessed information unless the control bit stored in the addressed location indicates that a valid transition vector is stored therein.
Claim 8
Dependent Claim
127 words
The method of claim 1 or 2 characterized in that said storing steps include: clearing information relating to a previous testing operation from the local memory in parallel; writing vector information into only those address locations of the local memory that relate to cycles in a testing procedure in which transitions occur in the operation of the data channel; writing an enable control bit into those address locations of the local memory that contain valid transition data; and by the steps of addressing a location in the local memory during each cycle of the testing procedure; and enabling a data channel control circuit to receive stored vector information only from those address locations in which a stored enable control bit indicates that valid transition data is stored.
Claim 9
Dependent Claim
62 words
The method of claim 7 characterized in that said data channel control circuit includes a register and said control bit controls a clock signal to said register so that said register is triggered by the clock signal to receive information from the local memory only when the control bit indicates a memory location containing a valid transition vector is presently being addressed.
Claim 10
Dependent Claim
33 words
The method of claim 7 or 8 characterized in that the step of clearing information in parallel includes performing a number of memory write cycles equal to the depth of the local memory.
Claim 11
Dependent Claim
154 words
A circuit for controlling the operation of a data channel in a digital test device characterized by: a memory having a storage location for each cycle in a test procedure, said memory containing test vectors describing transitions to be made in the operation to be performed in the data channel at the storage locations corresponding to the test cycles in which the transitions are to take place, and a control bit in each storage location indicative of whether the storage location contains a valid transition vector; a data channel control circuit for controlling the operation of the data channel in accordance with the vector information stored in the memory; means for addressing a storage location during each successive cycle of a test procedure; and means responsive to the control bit stored in an addressed storage location for selectively enabling the data channel control circuit to receive the vector information in the addressed storage location.
Claim 12
Dependent Claim
154 words
A circuit for controlling the operation of a data channel in a digital test device characterized by: a memory having a storage location for each cycle in a test procedure, said memory containing test vectors describing transitions to be made in the operation to be performed in the data channel at the storage locations corresponding to the test cycles in which the transitions are to take place, and a control bit in each storage location indicative of whether the storage location contains a valid transition vector; a data channel control circuit for controlling the operation of the data channel in accordance with the vector information stored in the memory; means for addressing a storage location during each successive cycle of a test procedure; and means responsive to the control bit stored in an addressed storage location for selectively enabling the data channel control circuit to receive the vector information in the addressed storage location.
Claim 13
Dependent Claim
40 words
The circuit of claim 10 characterized in that said data channel control circuit includes a register, and said selective enabling means includes means for controlling a clock signal that enables said register to read the information stored in said memory.
Claim 14
Dependent Claim
31 words
The circuit of claim 10 or 11 characterized in that said selective enabling means comprises a gate for gating the clock signal to said register in response to the control bit.
Claim 15
Dependent Claim
28 words
The circuit of claim 11 or 12 characterized in that the control bit is applied as an enable signal to a clock circuit for generating the clock signal.
References Cited (Backward Citations)
GB2020439A
Cited
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