Patent US5025182A successfully refreshed from Google Patents.
US5025182A
Expired / Lapsed
US
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Digital apparatus for generating gating signals in response to a data signal
Assignee: Advanced Micro Devices Inc
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Filing: 1990-08-31
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Granted: 1991-06-18
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Expires: 2010-08-31
Abstract
Abstract An apparatus for generating first and second digital gating signals in response to a data signal. The first gating signal and the second gating signal are selectively isolatable from each other according to a state signal. The apparatus comprises a gate signal circuit for receiving the data signal and generating the first gating signal on a first line and the second gating signal on a second line. A state input circuit receives the state signal and distributes a plurality of control signals representative of the state signal to the apparatus. An override circuit imposes values on the first and second lines in response to the control signals. The override circuit electrically isolates the first line from the second line in response to the control signals. In a preferred embodiment, the apparatus also includes a DRIVE-HIGH circuit for controlling the override circuit. The DRIVE-HIGH circuit is configured to operate when the state signal is in a first state to detect when a drive signal goes high, and responds to the driver signal going high by gating the override circuit appropriately to effect electrical disconnection of the first line and the second line. The DRIVE-HIGH circuit maintains such electrical isolation between the first line and the second line until the state signal changes to a second state.
Inventors
- 👤 Charles Farmer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 18:06
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/09425; H03K19/09429
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
163 words
A digital apparatus for generating digital gating signals in response to a data signal, said digital gating signals comprising a first gating signal and a second gating signal, said first gating signal and said second gating signal being selectively isolatable from each other according to a state signal; the apparatus comprising: a gate signal means for receiving said data signal and generating said first and second gating signals, said first gating signal being presented on a first line, said second gating signal being presented on a second line; a state input means for receiving said state signal and distributing a plurality of control signals to the apparatus, each of said plurality of control signals being representative of said state signal; and an override means for imposing values on said first line and said second line, said imposing being effected in response to said control signals, said override means electrically isolating said first line and said second line in response to said control signals.
Claim 2
Dependent Claim
163 words
A digital apparatus for generating digital gating signals in response to a data signal, said digital gating signals comprising a first gating signal and a second gating signal, said first gating signal and said second gating signal being selectively isolatable from each other according to a state signal; the apparatus comprising: a gate signal means for receiving said data signal and generating said first and second gating signals, said first gating signal being presented on a first line, said second gating signal being presented on a second line; a state input means for receiving said state signal and distributing a plurality of control signals to the apparatus, each of said plurality of control signals being representative of said state signal; and an override means for imposing values on said first line and said second line, said imposing being effected in response to said control signals, said override means electrically isolating said first line and said second line in response to said control signals.
Claim 3
Dependent Claim
93 words
An apparatus for generating digital gating signals in response to a data signal as recited in claim 1 wherein said gate signal means comprises a first and a second digital switching means for switching digital signals; said first and said second digital switching means commonly receiving said data signal at their respective gates; said first digital switching means being operatively connected as pull-up digital switch between a voltage source and said first line; said second digital switching means being operatively connected as a pulldown down digital switch between ground and said second line.
Claim 4
Dependent Claim
204 words
An apparatus for generating digital gating signals in response to a data signal as recited in claim 2 wherein said state input means comprises a first inverter; a second inverter; and first and second override switching means for effecting said imposing and said isolating; said first inverter receiving said state signal and generating a first inverter output, said second inverter receiving said first inverter output and generating a second inverter output; said first inverter output comprising a first control signal of said plurality of control signals, said second inverter output comprising a second control signal of said plurality of control signals; said first override switching means responding to said first control signal and said second override switching means responding to said second control signal to electrically isolate said first line from said second line, to impose a high signal on said first line, and to impose a low signal on said second line when said state signal is in a first state; said first override switching means responding to said first control signal and said second override switching means responding to said second control signal to electrically connect said first line and said second line when said state signal is in a second state.
Claim 5
Dependent Claim
129 words
An apparatus for generating digital gating signals in response to a data signal as recited in claim 3 wherein said first and second gating signals are provided to a driver circuit, said driver circuit generating a driver signal in response to said first and second gating signals, and wherein said state means comprises a drive-high means for controlling said override means, said drive-high means being configured to operate when said state signal is in a first state to detect when said driver signal goes high, said drive-high means responding to said driver signal going high by gating said override means appropriately to effect electrical connection of said first line and said second line, said drive-high means maintaining said electrical connection until said state signal changes to a second state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-17 | 1994-12-17 | 1995-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-17 | 1998-12-17 | 1999-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-17 | 2002-12-17 | 2003-06-18 | $7700.00 | Window Closed / Lapsed |