US5023485A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and circuitry for testing a programmable logic device
Assignee: Texas Instruments Inc
•
Filing: 1989-12-04
•
Granted: 1991-06-11
•
Expires: 2009-12-04
Abstract
Abstract A test configuration register (80) associated with a programmable memory device (88), wherein the signals at the outputs of the test configuration register force elements of the memory device into certain logic states to enable the device to be tested without programmning the device's logic array (22).
Inventors
- 👤 Frank J. Sweeney
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 07:53
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
99 words
Circuitry for synchronously or asynchronously testing the functions of a programmable logic device, said device including a plurality of elements responsive to logic signals and a plurality of input lines, said input lines forming a portion of a data flow path of said device when not in test mode, comprising: a test memory operable to receive, store and output a plurality of test configuration bits; and circuitry responsive to said test configuration bits for forcing said elements of the logic device into predetermined configurations while test signals are applied to at least one of said plurality of input lines.
Claim 2
Dependent Claim
99 words
Circuitry for synchronously or asynchronously testing the functions of a programmable logic device, said device including a plurality of elements responsive to logic signals and a plurality of input lines, said input lines forming a portion of a data flow path of said device when not in test mode, comprising: a test memory operable to receive, store and output a plurality of test configuration bits; and circuitry responsive to said test configuration bits for forcing said elements of the logic device into predetermined configurations while test signals are applied to at least one of said plurality of input lines.
Claim 3
Dependent Claim
35 words
The circuitry of claim 1 and further comprising a gate coupled to said memory and operable to output test configuration bits to said forcing circuitry responsive to a control signal applied to the logic device.
Claim 4
Dependent Claim
32 words
The circuitry of claim 1 wherein one of the elements comprises a true input buffer and wherein said forcing circuitry includes circuitry to disable the true input buffer of the logic device.
Claim 5
Dependent Claim
32 words
The circuitry of claim 1 wherein one of the elements comprises a false input buffer and wherein said forcing circuitry includes circuitry to disable the false input buffer of the logic device.
Claim 6
Dependent Claim
28 words
The circuitry of claim 1 wherein one of the elements comprises an output and wherein said forcing circuitry includes circuitry to enable the output of the logic device.
Claim 7
Dependent Claim
34 words
The circuitry of claim 1 wherein one of the elements comprises a sum-of-products term and wherein said forcing circuitry includes circuitry to force the logical state of the sum-of-product term of the logic device.
Claim 8
Dependent Claim
32 words
The circuitry of claim 1 wherein one of the elements comprises a feedback true buffer and wherein said forcing circuitry includes circuitry to disable the feedback true buffer of the logic device.
Claim 9
Dependent Claim
32 words
The circuitry of claim 1 wherein one of the elements comprises a feedback false buffer and wherein said forcing circuitry includes circuitry to disable the feedback false buffer of the logic device.
Claim 10
Dependent Claim
30 words
The circuitry of claim 1 wherein one of the elements comprises an input/output buffer and wherein said forcing circuitry includes circuitry to disable the input/output buffer of the logic device.
Claim 11
Dependent Claim
32 words
The circuitry of claim 1 wherein one of the elements comprises a polarity switch and wherein said forcing circuitry includes circuitry to set and clear the polarity switch of the logic device.
Claim 12
Dependent Claim
31 words
The circuitry of claim 1 wherein one of the elements comprises a registered/combinatorial switch and wherein said forcing circuitry includes circuitry to select registered and combinatorial output of the logic device.
Claim 13
Dependent Claim
34 words
The circuitry of claim 1 wherein one of the elements comprises an asynchronous reset product term and wherein said forcing circuitry includes circuitry to disable the asynchronous reset product term of the logic device.
Claim 14
Dependent Claim
34 words
The circuitry of claim 1 wherein one of the elements comprises a synchronous preset product term and wherein said forcing circuitry includes circuitry to disable the synchronous preset product term of the logic device.
Claim 15
Independent Claim
78 words
A method for synchronously or asynchronously testing the functions of a programmable logic device, comprising the steps of: loading a test memory with test configuration bits; forcing a configuration of the logic device responsive to the signals at the outputs of said test memory; and applying a test signal to at least one input line of said device, wherein said input line forms a portion of a data flow path of said device when not in test mode.
Claim 16
Independent Claim
78 words
A method for synchronously or asynchronously testing the functions of a programmable logic device, comprising the steps of: loading a test memory with test configuration bits; forcing a configuration of the logic device responsive to the signals at the outputs of said test memory; and applying a test signal to at least one input line of said device, wherein said input line forms a portion of a data flow path of said device when not in test mode.
Claim 17
Dependent Claim
19 words
The method of claim 14 and further comprising the step of applying an enabling signal to the test memory.
Claim 18
Dependent Claim
23 words
The method of claim 14 wherein said loading step comprises the step of serially inputting the test configuration bits into the test memory.
Claim 19
Dependent Claim
55 words
The method of claim 14 wherein said forcing step comprises the steps of: latching the test configuration bits in the memory; gating the test configuration bits at the outputs of the memory with a test gating signal; and applying the test configuration bits from the outputs of the memory to elements of the logic device.
Claim 20
Dependent Claim
39 words
The method of claim 17 wherein said applying step comprises the steps of: forcing elements of the logic device into logic conditions determined by the test configuration bits; and testing the functionality and performance of the resulting logical configuration.
Claim 21
Dependent Claim
22 words
The method of claim 18 wherein said testing step further comprises the steps of testing the sum-of-products terms of the logic device.
Claim 22
Dependent Claim
32 words
The method of claim 18 wherein said testing step comprises the step of measuring T pd from every input terminal of the logic device to every input/output terminal of the logic device.
Claim 23
Dependent Claim
26 words
The method of claim 18 wherein said testing step comprises the step of measuring T su and T co for every output of the logic device.
Claim 24
Dependent Claim
32 words
The method of claim 18 wherein said testing step comprises the step of measuring T su from every input terminal of the logic device to every input/output terminal of the logic device.
Claim 25
Dependent Claim
35 words
The method of claim 18 wherein said testing step comprises the step of measuring T en and T dis from every input terminal of the logic device to every input/output terminal of the logic device.
Claim 26
Dependent Claim
36 words
The method of claim 18 wherein said testing step comprises the step of measuring T en and T dis for every input/output terminal of the logic device to every other input/output terminal of the logic device.
Claim 27
Dependent Claim
35 words
The method of claim 18 wherein said testing step comprises the step of measuring T pd for asynchronous reset from every input terminal of the logic device to every input/output terminal of the logic device.
Claim 28
Dependent Claim
35 words
The method of claim 18 wherein said testing step comprises the step of measuring T su for synchronous preset from every input terminal of the logic device to every input/output terminal of the logic device.
Claim 29
Dependent Claim
104 words
A programmable logic device comprising: a plurality of elements responsive to logic signals; a plurality of input lines operable for inputting logic signals to said device, said plurality of input lines further operable for inputting test signals to said device, wherein said input lines form a portion of a data flow path of said device when not in test mode; a test memory operable to receive, store and output said test configuration bits; and circuitry responsive to said test configuration bits for forcing said elements of the logic device into predetermined configurations while said test signals are applied to said plurality of input lines.
Claim 30
Dependent Claim
104 words
A programmable logic device comprising: a plurality of elements responsive to logic signals; a plurality of input lines operable for inputting logic signals to said device, said plurality of input lines further operable for inputting test signals to said device, wherein said input lines form a portion of a data flow path of said device when not in test mode; a test memory operable to receive, store and output said test configuration bits; and circuitry responsive to said test configuration bits for forcing said elements of the logic device into predetermined configurations while said test signals are applied to said plurality of input lines.
Claim 31
Dependent Claim
38 words
The programmable logic device of claim 27 and further comprising a gate coupled to said test memory and operable to output test configuration bits to said configuring circuitry responsive to a control signal applied to the logic device.
Claim 32
Dependent Claim
35 words
The programmable logic device of claim 27 wherein one of the elements comprises a true input buffer and wherein said configuring circuitry includes circuitry to disable the true input buffer of the programmable logic device.
Claim 33
Dependent Claim
35 words
The programmable logic device of claim 27 wherein one of the elements comprises a false input buffer and wherein said configuring circuitry includes circuitry to disable the false input buffer of the programmable logic device.
Claim 34
Dependent Claim
31 words
The programmable logic device of claim 27 wherein one of the elements comprises an output and wherein said configuring circuitry includes circuitry to disable the output of the programmable logic device.
Claim 35
Dependent Claim
37 words
The programmable logic device of claim 27 wherein one of the elements comprises a sum-of-products term and wherein said configuring circuitry includes circuitry to force the logical state of the sum-of-products term of the programmable logic device.
Claim 36
Dependent Claim
34 words
The programmable logic device of claim 27 wherein one of the elements comprises feedback true buffer and wherein said configuring circuitry includes circuitry to disable the feedback true buffer of the programmable logic device.
Claim 37
Dependent Claim
34 words
The programmable logic device of claim 27 wherein one of the elements comprises feedback false buffer and wherein said configuring circuitry includes circuitry to disable the feedback false buffer of the programmable logic device.
Claim 38
Dependent Claim
33 words
The programmable logic device of claim 27 wherein one of the elements comprises an input/output buffer and wherein said configuring circuitry includes circuitry to disable the input/output buffer of the programmable logic device.
Claim 39
Dependent Claim
33 words
The programmable logic device of claim 27 wherein one of the elements comprises a polarity switch and wherein said configuring circuitry includes circuitry to disable the polarity switch of the programmable logic device.
Claim 40
Dependent Claim
36 words
The programmable logic device of claim 27 wherein one of the elements comprises a registered/combinatorial switch and wherein said configuring circuitry includes circuitry to force the state of the registered/combinatorial switch of the programmable logic device.
Claim 41
Dependent Claim
37 words
The programmable logic device of claim 27 wherein one of the elements comprises an asynchronous reset product term and wherein said configuring circuitry includes circuitry to disable the asynchronous reset product term of the programmable logic device.
Claim 42
Dependent Claim
37 words
The programmable logic device of claim 27 wherein one of the elements comprises a synchronous preset product term and wherein said configuring circuitry includes circuitry to disable the synchronous reset product term of the programmable logic device.
References Cited (Backward Citations)
US4517672A
Cited
US4625311A
Cited
US4879688A
Cited
US4740919A
Cited
US4857773A
Cited
US4780628A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-10 | 1994-12-10 | 1995-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-10 | 1998-12-10 | 1999-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-10 | 2002-12-10 | 2003-06-11 | $7700.00 | Window Closed / Lapsed |