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US5023197A Expired / Lapsed US ⏱️ 0.0 years remaining

Manufacturing process of mesa SOI MOS transistor

Assignee: Ministère des Postes Télégraphes et Téléphones
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Filing: 1990-08-15
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Granted: 1991-06-11
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Expires: 2010-08-15
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Abstract

Abstract A method for manufacturing a MOS transistor formed in a silicon block on insulator with convex rounded up edges, initially consisting in etching the block in a thin layer of silicon on insulator (SOI). In this method etching of the block comprises the following steps: forming at the position where it is desired to obtain the block a mask layer portion (3) having a thickness slightly higher than that of the SOI; depositing a second silicon layer (11) having a predetermined thickness; and anisotropically etching silicon until said insulator is apparent outside the mask layer portion.

Inventors

  • 👤 Michel Haond
  • 👤 Jean Galvier

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 01:05
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D86/00; H10D86/01; H10P; H10P50/00; H10P50/71; Y; Y10; Y10S; Y10S148/00; Y10S148/051; Y10S148/161; Y10S438/00; Y10S438/978

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 100 words
A method for manufacturing a MOS transistor in a silicon on insulator block wherein said block exhibits convex rounded up edges, initially consisting in etching the block in a thin layer of single crystal silicon on insulator, wherein etching of the block comprises the following steps: forming at the position where it is desired to obtain the block a mask layer portion (3) having a thickness slightly larger than that of the thin silicon on insulator layer; depositing a second silicon layer (11) having a predetermined thickness; and anisotropically etching silicon until said insulator is apparent outside said mask portion.
Claim 2
Independent Claim 100 words
A method for manufacturing a MOS transistor in a silicon on insulator block wherein said block exhibits convex rounded up edges, initially consisting in etching the block in a thin layer of single crystal silicon on insulator, wherein etching of the block comprises the following steps: forming at the position where it is desired to obtain the block a mask layer portion (3) having a thickness slightly larger than that of the thin silicon on insulator layer; depositing a second silicon layer (11) having a predetermined thickness; and anisotropically etching silicon until said insulator is apparent outside said mask portion.
Claim 3
Dependent Claim 29 words
A method according to claim 1, wherein the insulator on which is formed said thin silicon layer is constituted by a silicon oxide layer formed on a silicon wafer.
Claim 4
Dependent Claim 18 words
A method according to claim 1, wherein said mask is constituted by a silicon oxide/silicon nitride/silicon oxide sandwich.
Claim 5
Dependent Claim 16 words
A method according to claim 1, wherein said mask is constituted by a silicon oxide/silicon sandwich.
Claim 6
Dependent Claim 30 words
A method according to claim 3, further comprising the step consisting in implanting a dopant in the silicon block while it is still masked, in order to overdop its edges.
Claim 7
Dependent Claim 17 words
A method according to claim 1, wherein the mask is constituted by a silicon oxide/silicon/silicon oxide sandwich.
Claim 8
Dependent Claim 23 words
A method according to claim 6, further comprising the step consisting in implanting a dopant after formation of said mask layer portion (3).
Claim 9
Dependent Claim 55 words
A method according to claim 5, wherein the anisotropic etching step according to claim 1 is subdivided into the following steps: etching the silicon until the upper layer of the mask is apparent; etching the upper silicon layer of the mask; and etching the silicon until said insulator is apparent outside the mask layer portion.

References Cited (Backward Citations)

US4349408A Cited
US4394182A Cited
JPS60234326A Cited
US4637836A Cited
US4753896A Cited
US4716128A Cited
US4735679A Cited
US4916086A Cited
US4903108A Cited
US4906587A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-06-10 1994-12-10 1995-06-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-06-10 1998-12-10 1999-06-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-06-10 2002-12-10 2003-06-11 $7700.00 Window Closed / Lapsed

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