Integrator circuit

Claim 2

A bilinear integrator circuit for sampled signal currents comprising: first and second inputs and an output, means for connecting the first input to an input of a first current memory cell which is arranged to store a current applied in a first portion of each sampling period and to reproduce a current, whose magnitude is dependent on the magnitude of the applied current, at an output of said first current memory cell during a second portion of that or a succeeding sample period, means for connecting the second input to an input of a second current memory cell which is arranged to store a current applied to its input in the second portion of each sampling period and to reproduce at each of a first and second output of the second current memory cell a current, whose magnitude is dependent upon that of the current applied to its input, during the first portion of that or a succeeding sampling period, means for connecting the first output of the second current memory cell to the input of the first current memory cell, means for connecting the output of the first current memory cell to the input of the second current memory cell, and means for connecting the second output of the second current memory cell to the output of the integrator circuit.

Claim 3

An integrator circuit as claimed in claim 1 wherein the second current memory cell produces an output current at its first output equal to B times the current applied to its input, where B is less than one.

Claim 4

An integrator circuit as claimed in claim 1 or claim 2 further comprising means coupled to the first current memory cell input for adding a bias current to the current applied to the first input of the integrator circuit, and means for subtracting appropriately scaled bias currents from first and second output currents of the second current memory cell so that an output current produced by the integrator circuit contains no bias current component.

Claim 5

An integrator circuit as claimed in claim 1 wherein the first current memory cell comprises a diode connected field effect transistor connected to its input, means connected a gate electrode of said field effect transistor through a switch to a gate electrode of a second similar field effect transistor, the first and second field effect transistors having source electrodes connected to a common point, said output of the first current memory cell being connected to a drain electrode of the second transistor, a capacitor connected between the source and gate electrodes of the second transistor, and means for closing the switch only during the first portion of each sampling period.

Claim 6

An integrator circuit as claimed in claim 3 wherein the first current memory cell comprises a first switch connected between its input and a drain electrode of a field effect transistor, a second switch connected between the gate and drain electrodes of the transistor, a capacitor connected between the gate and source electrodes of the transistor, a third switch connected between the drain electrode of the transistor and its output means for closing the first and second switches only during the first portion of each sampling period, and means for closing the third switch only during the second portion of each sampling period.

Claim 7

A bilinear integrator circuit as claimed in claim 1 for integrating a differential input current and for producing a differential output current, the integrator circuit further comprising a second output, a third current memory cell, a fourth current memory cell, means for coupling an output of the third current memory cell to an input of the fourth current memory cell, means for coupling a first output of the fourth current memory cell to an input of the third current memory cell, means for connecting the first input of the integrator circuit to the input of the first current memory cell during the first portion of each sampling period, means for connecting the first input of the integrator circuit to the input of the fourth current memory cell during the second portion of each sampling period, means for connecting the second input of the integrator circuit to the input of the third current memory cell during the first portion of each sampling period, means for connecting the second input of the integrator circuit to the input of the second current memory cell during the second portion of each sampling period, means for connecting the second output of the second current memory cell to the first output of the integrator circuit, and means for connecting a second output of the fourth memory cell to the second output of the integrator circuit.

Claim 8

An integrator circuit as claimed in claim 6 further comprising means for adding bias currents to the currents applied to the inputs of the first and third current memory cells and means for subtracting appropriately scaled bias currents from the outputs of the second and fourth current memory cells so that the output differential currents contain no bias current component.

Claim 9

An integrator circuit as claimed in claim 7 wherein all transistors which conduct signal currents comprise as n-channel field effect transistors.

Claim 10

An integrator circuit as claimed in claim 3 wherein the first current memory cell comprises a diode connected field effect transistor connected to its input, means connecting a gate electrode of said field effect transistor through a switch to a gate electrode of a second similar filed effect transistor, the first and second filed effect transistors having source electrodes connected to a common point, said output of the first current memory cell being connected to a drain electrode of the second transistor, a capacitor connected between the source and gate electrodes of the second transistor, and means for closing the switch only during the first portion of each sampling period.

Claim 11

An integrator circuit as claimed in claim 1 wherein the first current memory cell comprises a first switch connected between its input and a drain electrode of a field effect transistor, a second switch connected between the gate and drain electrodes of the transistor, a capacitor connected between the gate and source electrodes of the transistor, a third switch connected between the drain electrode of the transistor and its output, means for closing the first and second switches only during the first portion of each sampling period, and means for closing the third switch only during the second portion of each sampling period.

Claim 12

An integrator circuit as claimed in claim 2 wherein the first current memory cell comprises a first switch connected between its input and drain electrode of a field effect transistor, a second switch connected between the gate and drain electrodes of the transistor, a capacitor connected between the gate and source electrodes of the transistor, a third switch connect between the drain electrode of the transistor and its output, means for closing the first and second switches only during the first portion of each sampling period, and means for closing the third switch only during the second portion of each sampling period.

Claim 13

A bilinear integrator circuit as claimed in claims 2 or 4 for integrating a differential input current and for producing a differential output current, the integrator circuit further comprising a second output, a third current memory cell, a fourth current memory cell, means for coupling an output of the third current memory cell to an input of the fourth current memory cell, means for coupling a first output of the fourth current memory cell to an input of the third current memory cell, means for connecting the first input of the integrator circuit to the input of the first current memory cell during the first portion of each sampling period, means for connecting the first input of the integrator circuit to the input of the fourth current memory cell during the second portion of each sampling period, means for connected the second input of the integrator circuit to the input of the third current memory cell during the first portion of each sampling period, means for connecting the second input of the integrator circuit to then put of the second current memory cell during the second portion of each sampling period, means for connecting the second output of the second current memory cell to the first output of the integrator circuit, and means for connecting a second output of the fourth memory cell to the second output of the integrator circuit.

Claim 14

An integrator circuit as claimed in claim 12 further comprising means for adding bias currents to currents applied to the inputs of the first and third current memory cells and means for substrating appropriately scaled bias currents from the outputs of the second and fourth current memory cells so that the output differential currents contain no bias current component.

Claim 15

A bilinear integrator circuit as claimed in claim 10 for integrating a differential input current and for producing a differential output current, the integrator circuit further comprising a second output, a third current memory cell, a fourth current memory cell means for coupling an output of the third current memory cell to an input of the fourth current memory cell, means for coupling a first output of the fourth current memory cell to an input of the third current memory cell, means for connecting the first input of the integrator circuit to the input of the first current memory cell during the first portion of each sampling period, means for connected the first input of the integrator circuit to the input of the fourth current memory cell during the second portion of each sampling period, means for connecting the second input of the integrator circuit to the input of the third current memory cell during the first portion of each sampling period, means for connecting the second input of the integrator circuit to the input of the second current memory cell during the second portion of each sampling period, means for connecting the second output of the second current memory cell to the first output of the integrator circuit, and means for connecting a second output of the fourth memory cell to the second output of the integrator circuit.

Claim 16

An integrator circuit as claimed in claim 14 further comprising means for adding bias currents to currents applied to the inputs of the first and third current memory cells and means for subtracting appropriately scaled bias currents from the outputs of the second and fourth current memory cells so that the output differential currents contain no bias current component.

Claim 17

An integrator circuit as claimed in claim 1, 2, 4 or 6 wherein all transistors which conduct signal currents comprise n-channel field effect transistors.

Claim 18

An integrator circuit as claimed in claim 2 wherein the first current memory cell comprises a diode connected field effect transistor connected to its input, means connecting a gate electrode of said field effect transistor through a switch to a gate electrode of a second similar field effect transistor, the first and second field effect transistors having source electrodes connected to a common point, said output of the first current memory cell being connected to a drain electrode of the second transistor, a capacitor connected between the source and gate electrodes of the second transistor, and means for closing the switch only during the first portion of each sampling period.

Claim 19

An integrator circuit as claimed in claim 1 further comprising a first current source coupled via a first switch to a field effect transistor in said first current memory cell thereby to add a DC bias current t the current applied to the first input of the integrated circuit, and means for subtracting first and second scaled DC bias currents from first and second output currents, respectively, of the second current memory cell so that a bidirectional output current is produced at the integrator circuit output, said output current being substantially devoid of any bias current component.