Device for synchronizing a pseudo-binary signal with a regenerated clock signal having phase jumps

Claim 1

A device for synchronizing a pseudo-binary signal with a clock signal into an outgoing synchronized signal, said pseudo binary signal having a nominal period and comprising first and second binary elements, each of said first binary elements being signalled by first and second complementary logic levels respectively substantially during first and second successive nominal half-periods, and each of said second binary elements being signalled by said second logic level substantially during a nominal period, a first binary element always being flanked by two second binary elements, thereby defining logic level transitions from said second logic level to said first logic level located between successive second and first binary elements, said clock signal having a period substantially lower than said nominal period and offering periodical phase jumps for said clock signal to have a mean period equal to said nominal period, thereby defining active clock transitions from one of said logic levels to the other logic level at the beginning of said period of said clock signal, and said clock signal phase jumps having a constant amplitude that is at most substantially equal to said clock signal period, said device comprising: means receiving said pseudo-binary signal for providing a first logic signal having states alternately in said second and first logic levels in response to said logic level transitions in said pseudo-binary signal, means controlled by the clock signal for phasing said logic level transitions in said first logic signal with active clock transitions in said clock signal, thereby deriving a phased logic signal, and means controlled by said clock signal for supplying said outgoing synchronized signal with pulses which are at said first logic level and which have a width calibrated as a function of the period of said clock signal and which are respectively derived in response to the logic level transitions in said phased logic signal.

Claim 2

A device for synchronizing a pseudo-binary signal with a clock signal into an outgoing synchronized signal, said pseudo binary signal having a nominal period and comprising first and second binary elements, each of said first binary elements being signalled by first and second complementary logic levels respectively substantially during first and second successive nominal half-periods, and each of said second binary elements being signalled by said second logic level substantially during a nominal period, a first binary element always being flanked by two second binary elements, thereby defining logic level transitions from said second logic level to said first logic level located between successive second and first binary elements, said clock signal having a period substantially lower than said nominal period and offering periodical phase jumps for said clock signal to have a mean period equal to said nominal period, thereby defining active clock transitions from one of said logic levels to the other logic level at the beginning of said period of said clock signal, and said clock signal phase jumps having a constant amplitude that is at most substantially equal to said clock signal period, said device comprising: means receiving said pseudo-binary signal for providing a first logic signal having states alternately in said second and first logic levels in response to said logic level transitions in said pseudo-binary signal, means controlled by the clock signal for phasing said logic level transitions in said first logic signal with active clock transitions in said clock signal, thereby deriving a phased logic signal, and means controlled by said clock signal for supplying said outgoing synchronized signal with pulses which are at said first logic level and which have a width calibrated as a function of the period of said clock signal and which are respectively derived in response to the logic level transitions in said phased logic signal.

Claim 12

A device for synchronizing a pseudo-binary signal with a clock signal into an outgoing synchronized signal, said pseudo-binary signal having a nominal period and comprising first and second binary elements, each of said first binary elements being signalled by first and second complementary logic levels respectively substantially during first and second successive nominal half-periods, and each of said second binary elements being signalled by said second logic level substantially during a nominal period, a first binary elements always being flanked by two second binary elements, thereby defining logic level transitions from said second logic level to said first logic level located between successive second and first binary elements, said clock signal having a period substantially lower than said nominal period and offering periodical phase jumps for said clock signal to have a mean period equal to said nominal period, thereby defining active clock transitions from one of said logic levels to the other logic level at the beginning of said period of said clock signal, and said clock signal phase jumps having a constant amplitude that is at most substantially equal to said clock signal period, said device comprising: a first bistable flip-flop having a clock input receiving said pseudo-binary signal, an inverse output and a data input connected to one another, and a direct output providing a first logic signal having states alternately in said second and first logic levels in response to said logic level transitions in said pseudo-binary signal, a second bistable flip-flop having a clock input receiving said clock signal, a data input connected to said direct output of said first flip-flop, and an output supplying a phased logic signal resulting from phasing of said logic level transitions in said first logic signal with active clock transitions in said clock signal, a third bistable flip-flop having a clock input receiving said clock signal and a data input receiving said phased logic signal, and an Exclusive-OR gate having an input receiving said phased signal and another input connected to a direct output of said third flip-flop and an output supplying said outgoing synchronized signal with pulses which are at said first logic level and which have a calibrated width substantially equal to the period of said clock signal and which are respectively derived in response to the logic level transitions in said phased logic signal.

Claim 13

A device for synchronizing a pseudo-binary signal with a clock signal into an outgoing synchronized signal, said pseudo-binary signal having a nominal period and comprising first and second binary elements, each of said first binary elements being signalled by first and second complementary logic levels respectively substantially during first and second successive nominal half-periods, and each of said second binary elements being signalled by said second logic level substantially during a nominal period, a first binary elements always being flanked by two second binary elements, thereby defining logic level transitions from said second logic level to said first logic level located between successive second and first binary elements, said clock signal having a period substantially lower than said nominal period and offering periodical phase jumps for said clock signal to have a mean period equal to said nominal period, thereby defining active clock transitions from one of said logic levels to the other logic level at the beginning of said period of said clock signal, and said clock signal phase jumps having a constant amplitude that is at most substantially equal to said clock signal period, said device comprising: a first bistable flip-flop having a clock input receiving said pseudo-binary signal, an inverse output and a data input connected to one another, and a direct output providing a first logic signal having states alternately in said second and first logic levels in response to said logic level transitions in said pseudo-binary signal, a second bistable flip-flop having a clock input receiving said clock signal, a data input connected to said direct output of said first flip-flop, and an output supplying a phased logic signal resulting from phasing of said logic level transitions in said first logic signal with active clock transitions in said clock signal, a third bistable flip-flop having a clock input receiving said clock signal and a data input receiving said phased logic signal, and an Exclusive-OR gate having an input receiving said phased signal and another input connected to a direct output of said third flip-flop and an output supplying said outgoing synchronized signal with pulses which are at said first logic level and which have a calibrated width substantially equal to the period of said clock signal and which are respectively derived in response to the logic level transitions in said phased logic signal.