Synchronizing circuit in a plesiochronous digital signal multiplexer

Claim 1

A synchronizing circuit in a multiplexer multiplexing N plesiochronous digital signals having a nominal timing frequency substantially less than a predetermined timing frequency h/(2N) into a resultant signal having a timing frequency h/2, said synchronizing circuit comprising an oscillator supplying a local clock signal, means receiving said local clock signal and on of said plesiochronous signals coded in a bipolar code for regenerating a timing signal peculiar to said plesiochronous signal and having significant times synchronous with significant times of said local clock signal, said regenerated timed signal having a mean timing frequency equal to said nominal timing frequency, transcoding means receiving said plesiochronous signal and said regenerated timing signal for transcoding said plesiochronous signal into a reshaped binary signal timed by said regenerated timing signal, and storing and justifying means receiving said reshaped binary signal, said regenerated timing signal and said predetermined timing frequency for storing said reshaped binary signal under the control of said regenerated timing signal into a stored signal and for justifying said stored signal as a function of phase difference between said regenerated timing signal and said predetermined timing frequency into a justified signal timed at said predetermined timing frequency, and said timing signal regenerating means comprising logic means for periodically deleting a pulse in said local clock signal in terms of a phase-shift between said regenerated timing signal and said local clock signal to produce an intermediate clock signal having a periodically deleted pulse comparatively with said local clock signal, and logic frequency dividing means for dividing said intermediate clock signal in frequency by 2N to derive said regenerated timing signal.