US3916084A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Compact-bi-phase pulse coded modulation decoder
Assignee: National Aeronautics and Space Administration
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Filing: 1974-12-26
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Granted: 1975-10-28
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Expires: 1994-12-26
Abstract
Abstract An apparatus for extracting and generating a clock pulse train from a pulse coded data train. The apparatus includes a filter circuit for receiving the pulse coded data train. A first setreset flip-flop is provided for receiving the signals from the pulse coded train. Coupled to the output of the first flip-flop is a means for generating a triggering pulse responsive to the occurrence of data within the train. A pulse gate activated by said triggering pulse for causing the data from said pulse coded data train to be stored in a second flip-flop. A clock pulse generating means is coupled between the outputs of the first and second flip-flops for generating a continuous stream of clock pulses which are synchronized with the incoming pulse coded data train.
Inventors
- 👤 Pierce C Toole
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:00
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
235 words
An apparatus for extracting and generating a clock pulse train from a pulse coded data train comprising: a. a filter circuit for receiving said pulse coded data train; b. a first set-reset flip-flop coupled to an output of said filter circuit for receiving signals corresponding to said data train therefrom, said first flip-flop having a Q and Q output; c. a pulse gate having a pair of inputs, a pair of outputs and a trigger input, said inputs being coupled to said Q and Q outputs of said first set-reset flip-flop; d. means coupled between said Q and Q outputs of said first setreset flip-flop and said trigger input of said pulse gate for generating and supplying a gating pulse to said trigger input each time a change in data appears in said data train; e. a second set-reset flip-flop having a pair of inputs coupled to said pair of outputs of said pulse gate and Q and Q outputs so that said pulse gate gates signals from said Q and Q outputs of said first flip-flop to said Q and Q outputs of said second flip-flop each time a change of data appears in said data train; f. a clock pulse generating means coupled to said Q and Q outputs of said first flip-flop, and to said Q and Q outputs of said second set-reset flip-flop for generating a sequential chain of clock pulses.
Claim 2
Independent Claim
235 words
An apparatus for extracting and generating a clock pulse train from a pulse coded data train comprising: a. a filter circuit for receiving said pulse coded data train; b. a first set-reset flip-flop coupled to an output of said filter circuit for receiving signals corresponding to said data train therefrom, said first flip-flop having a Q and Q output; c. a pulse gate having a pair of inputs, a pair of outputs and a trigger input, said inputs being coupled to said Q and Q outputs of said first set-reset flip-flop; d. means coupled between said Q and Q outputs of said first setreset flip-flop and said trigger input of said pulse gate for generating and supplying a gating pulse to said trigger input each time a change in data appears in said data train; e. a second set-reset flip-flop having a pair of inputs coupled to said pair of outputs of said pulse gate and Q and Q outputs so that said pulse gate gates signals from said Q and Q outputs of said first flip-flop to said Q and Q outputs of said second flip-flop each time a change of data appears in said data train; f. a clock pulse generating means coupled to said Q and Q outputs of said first flip-flop, and to said Q and Q outputs of said second set-reset flip-flop for generating a sequential chain of clock pulses.
Claim 3
Dependent Claim
112 words
The apparatus as set forth in claim 1 wherein: said clock pulse generating means includes; a. a first and second AND gate each having a pair of inputs and an output; b. means for coupling said Q outputs of said first and second flip-flop to said inputs of said first AND gate; c. means for coupling said Q outputs of said first and second flip-flop to said inputs of said second flip-flop, and d. an OR gate having an output and a pair of inputs each of which is coupled to an output of said first and second AND gate; whereby said clock pulses appear on said output of said OR gate.
Claim 4
Dependent Claim
46 words
The apparatus as set forth in claim 1 wherein said means for generating a gating pulse includes: a. a retriggerable one-shot multivibrator, and b. means for resetting said retriggerable one-shot multivibrator for generating a gating pulse each time a data change appears in said data train.
Claim 5
Dependent Claim
30 words
The apparatus as set forth in claim 3 wherein said means for resetting said retriggerable one-shot multivibrator is a capacitor that discharges responsive to data appearing in said data train.
References Cited (Backward Citations)
US3663883A
Cited
US3593044A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-10-27 | 1979-04-28 | 1979-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-10-27 | 1983-04-28 | 1983-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-10-27 | 1987-04-28 | 1987-10-28 | $7700.00 | Window Closed / Lapsed |