Discriminator circuit for recorded modulated binary data signals

Claim 1

A discriminator circuit for separating clock pulses and data pulses from input data, said discriminator circuit including input means for providing input data in a pulse train including clock pulses and data pulses; circuit means having an input terminal and an output terminal and connected to said input means for generating data window gate signals by the succeeding clock pulse of two adjacent clock pulses in the input data pulse train when no data pulse exists between said two clock pulses, generating the data window gate signals by the data pulse when a data pulse exists between said two clock pulses, and separating the clock pulses and the data pulses from the input data pulse train by the data window gate signals, said circuit means comprising delay means, a flip flop having a set input, a reset input, a set condition and a reset condition, a first gate circuit having an output terminal, an input terminal connected to the input means through the delay means and another input terminal connected to said flip flop and switched to conductive condition by data pulses derived from the input data through the delay means when said flip flop is in its set condition and means for supplying data pulses to the input terminal of said first gate circuit so that said data pulses are transferred by said first gate circuit when said first gate circuit is in conductive condition; and output means connected to the output terminal Of said circuit means for providing clock pulses and data pulses detected by said discriminator circuit.