Patent US5013944A successfully refreshed from Google Patents.
US5013944A
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US
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Programmable delay line utilizing measured actual delays to provide a highly accurate delay
Assignee: International Business Machines Corp
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Filing: 1989-04-20
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Granted: 1991-05-07
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Expires: 2009-04-20
Abstract
Abstract A method of operating a delay circuit to impose a selected delay on an electronic signal the delay circuit comprising a plurality of delay stages and means for directing the electronic signal through selected ones of the delay stages, the method comprising the steps of: measuring the actual signal delay through each of the delay stages; and selecting, based on the signal delays obtained in the measuring step, the delay stages through which the electronic signal is directed.
Inventors
- 👤 Jeffrey H. Fischer
- 👤 Lawrence J. Grasso
- 👤 Dale E. Hoffman
- 👤 Daniel E. Skooglund
- 👤 Diane K. Young
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:48
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/131; H03K5/135; H03K2005/00013; H03K2005/00078; H03K2005/00097; H03K2005/00104; H03K2005/0015; H03K2005/00234; H03K2005/00247; H03K2005/00254
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
97 words
A method of operating a delay circuit to impose a selected delay on an electric signal, said delay circuit comprising a plurality of delay stages and means for directing said electronic signal serially through selected ones of said delay stages, said method comprising the steps of: providing said plurality of delay stages each having at least one substantially fixed but not precisely known delay; measuring the actual signal delay through each of said delay stages; and selecting, based on the signal delays obtained in said measuring step, the delay stages through which said electronic signals is directed.
Claim 2
Independent Claim
97 words
A method of operating a delay circuit to impose a selected delay on an electric signal, said delay circuit comprising a plurality of delay stages and means for directing said electronic signal serially through selected ones of said delay stages, said method comprising the steps of: providing said plurality of delay stages each having at least one substantially fixed but not precisely known delay; measuring the actual signal delay through each of said delay stages; and selecting, based on the signal delays obtained in said measuring step, the delay stages through which said electronic signals is directed.
Claim 3
Dependent Claim
48 words
A method in accordance with claim 1 wherein said selecting step includes the steps of: calculating the signal path which will provide an actual delay closest to said selected delay; and directing said electronic signal through the delay stages constituting the signal path determined in said calculating step.
Claim 4
Independent Claim
125 words
A method of operating a programmable delay circuit to impose a selected delay on an electronic signal, said delay circuit comprising a plurality of delay stages, each of said delay stages including first and second signal paths for said electronic signal, said first signal path having a reference delay, said second signal path having said reference delay plus an additional delay, said method comprising the steps of: providing said plurality of delay stages, each of said second signal paths having a substantially fixed but not precisely known additional delay; measuring the actual additional delay through each of said second signal paths; and selecting, based on the additional delays obtained in said measuring step, the first or second signal path through each of said delay stages.
Claim 5
Independent Claim
125 words
A method of operating a programmable delay circuit to impose a selected delay on an electronic signal, said delay circuit comprising a plurality of delay stages, each of said delay stages including first and second signal paths for said electronic signal, said first signal path having a reference delay, said second signal path having said reference delay plus an additional delay, said method comprising the steps of: providing said plurality of delay stages, each of said second signal paths having a substantially fixed but not precisely known additional delay; measuring the actual additional delay through each of said second signal paths; and selecting, based on the additional delays obtained in said measuring step, the first or second signal path through each of said delay stages.
Claim 6
Dependent Claim
52 words
A method in accordance with claim 3 wherein said measuring step includes the steps of: measuring the total delay through all of said first signal paths; measuring the total delay through each individual one of said second signal paths; and calculating the actual additional delay through each of said second signal paths.
Claim 7
Dependent Claim
52 words
A method in accordance with claim 3 wherein said selecting step includes the steps of: determining which combination of the second signal paths in said delay stages will provide additional delays totaling closest to said selected delay; and directing said electronic signal through the second signal paths selected in said determining step.
Claim 8
Dependent Claim
60 words
A method in accordance with claim 3 wherein the additional delay in the second signal path of each of said delay stages is equal to approximately a power of 2 times a minimum delta delay, and further including the step of: providing at least two delay stages each including a second signal path having a lowest order 2° additional delay.
Claim 9
Dependent Claim
31 words
A method in accordance with claim 3 and further including the step of scaling the measured additional delays to compensate for changes in said delay circuit before performing said selecting step.
Claim 10
Independent Claim
140 words
A method of imposing a selected delay on an electronic signal comprising the steps of: providing a plurality N of delay stages, each of said N delay stages including first and second signal paths for said electronic signal, said first signal path having a minimum delay, said second signal path having said minimum delay plus an additional substantially fixed delay equal to approximately a power of 2 times a minimum delta delay, measuring the total delay through said first signal paths; measuring the delay through each individual one of said second signal paths; calculating the additional delay through each individual one of said second signal paths; determining which combination of said second signal paths will provide a total additional delay closest to said selected delay; and directing said electronic signal through the second signal paths selected in said determining step.
Claim 11
Independent Claim
140 words
A method of imposing a selected delay on an electronic signal comprising the steps of: providing a plurality N of delay stages, each of said N delay stages including first and second signal paths for said electronic signal, said first signal path having a minimum delay, said second signal path having said minimum delay plus an additional substantially fixed delay equal to approximately a power of 2 times a minimum delta delay, measuring the total delay through said first signal paths; measuring the delay through each individual one of said second signal paths; calculating the additional delay through each individual one of said second signal paths; determining which combination of said second signal paths will provide a total additional delay closest to said selected delay; and directing said electronic signal through the second signal paths selected in said determining step.
Claim 12
Dependent Claim
32 words
A method in accordance with claim 8 and further including the step of providing at least two of said delay stages including second signal paths having lowest order 2 0 additional delays.
Claim 13
Dependent Claim
45 words
A method in accordance with claim 9 wherein said delay circuit is fabricated on a single semiconductor chip and further including the step of scaling the calculated additional delays to compensate for variations in the calculated additional delays caused by such factors as thermal drift.
Claim 14
Dependent Claim
81 words
A delay circuit for imposing a selected delay on an electronic signal, comprising: a plurality of delay stages, each having at least one substantially fixed but not precisely known delay; means for directing said electronic signal through selected ones of said delay stages; means for measuring the actual signal delay through each of said delay stages; and means for selecting, based on the actual signal delays obtained in said measuring step, the delay stages through which said electronic signal is directed.
Claim 15
Dependent Claim
81 words
A delay circuit for imposing a selected delay on an electronic signal, comprising: a plurality of delay stages, each having at least one substantially fixed but not precisely known delay; means for directing said electronic signal through selected ones of said delay stages; means for measuring the actual signal delay through each of said delay stages; and means for selecting, based on the actual signal delays obtained in said measuring step, the delay stages through which said electronic signal is directed.
Claim 16
Dependent Claim
34 words
A delay circuit in accordance with claim 11 wherein said selecting means includes means for calculating a signal path through said delay stages which will provide an actual delay closest to said selected delay.
Claim 17
Dependent Claim
105 words
A programmable delay circuit for imposing a selected delay on an electronic signal, said delay circuit comprising: a plurality of delay stages, each of said delay stages including first and second signal paths for said electronic signal, said first signal path having a reference delay, said second signal path having said reference delay plus a substantially fixed but not precisely known additional delay; means for measuring the actual additional delay through each individual one of said second signal paths; and means for selecting, based on the additional delays obtained by said measuring means, the first or second signal path through each of said delay stages.
Claim 18
Dependent Claim
105 words
A programmable delay circuit for imposing a selected delay on an electronic signal, said delay circuit comprising: a plurality of delay stages, each of said delay stages including first and second signal paths for said electronic signal, said first signal path having a reference delay, said second signal path having said reference delay plus a substantially fixed but not precisely known additional delay; means for measuring the actual additional delay through each individual one of said second signal paths; and means for selecting, based on the additional delays obtained by said measuring means, the first or second signal path through each of said delay stages.
Claim 19
Dependent Claim
70 words
A delay circuit in accordance with claim 13 wherein said measuring means includes: means for measuring the total delay through all of said first signal paths in said delay circuit; means for measuring the total delay through said delay circuit when each of said second signal paths is selected one at a time; and means for calculating the actual additional delay through each individual one of said second signal paths.
Claim 20
Dependent Claim
51 words
A delay circuit in accordance with claim 13 wherein said selecting means includes: means for determining which combination of said second signal paths will provide a total additional delay closest to said selected delay; and means for directing said electronic signal through the second signal paths selected in said determining step.
Claim 21
Dependent Claim
58 words
A delay circuit in accordance with claim 13 wherein: the additional delay in the second signal path of each of said delay stages is equal to about a power of 2 times a minimum delta delay; and further including at least two delay stages each including a second signal path having a lowest order 2 0 additional delay.
Claim 22
Dependent Claim
31 words
A delay circuit in accordance with claim 13 and further including means for scaling the actual additional delays to compensate for changes in said delay circuit before performing said selecting step.
Claim 23
Dependent Claim
143 words
A delay circuit for imposing a selected delay on an electronic signal comprising: a plurality N of delay stages, each of said N delay stages including first and second signal paths for said electronic signal, said first signal path having a minimum delay, said second signal path having said minimum delay plus an additional, substantially fixed delay equal to about a power of two times a minimum delta delay; means for measuring the total delay through said first signal paths; means for measuring the individual delay through each of said second signal paths; means for calculating the additional delay through each of said second signal paths; means for determining which combination of said second signal paths will provide an additional delay closest to said selected delay; and means for directing said electronic signal through the second signal paths selected by said determining means.
Claim 24
Dependent Claim
143 words
A delay circuit for imposing a selected delay on an electronic signal comprising: a plurality N of delay stages, each of said N delay stages including first and second signal paths for said electronic signal, said first signal path having a minimum delay, said second signal path having said minimum delay plus an additional, substantially fixed delay equal to about a power of two times a minimum delta delay; means for measuring the total delay through said first signal paths; means for measuring the individual delay through each of said second signal paths; means for calculating the additional delay through each of said second signal paths; means for determining which combination of said second signal paths will provide an additional delay closest to said selected delay; and means for directing said electronic signal through the second signal paths selected by said determining means.
Claim 25
Dependent Claim
29 words
A delay circuit in accordance with claim 18 and further comprising at least two of said delay stages including second signal paths having lowest order 2 0 additional delays.
Claim 26
Dependent Claim
45 words
A delay circuit in accordance with claim 19 wherein said delay circuit is fabricated on a single semiconductor chip and further including means for scaling the calculated additional delays to compensate for changes in the calculated additional delays caused by such factors as thermal drift.
Claim 27
Dependent Claim
65 words
A delay circuit in accordance with claim 20 wherein said scaling means includes: means for generating a periodic signal fabricated on the same semiconductor chip as said delay circuit; means for measuring the frequency of said generating means; means for calculating scaling factors pursuant to changes in the frequency of said generating means; and means for applying said scaling factors to the measured additional delays.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-06 | 1994-11-05 | 1995-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-06 | 1998-11-05 | 1999-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-06 | 2002-11-05 | 2003-05-07 | $7700.00 | Window Closed / Lapsed |