US5012435A
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Multiple event timer circuit
Assignee: International Business Machines Corp
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Filing: 1988-11-17
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Granted: 1991-04-30
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Expires: 2008-11-17
Abstract
Abstract A timer including a counter circuit that continuously provides an output of an iteratively increasing sequence of bits. The timer includes a timeout data circuit that forms a timeout data word from a specified time period and a first counter circuit output. A register is provided that stores the timeout data word at an address formed from a second counter circuit output. A comparison circuit is provided that compares each counter output with a timeout data word at the address formed from that counter output and provides a timeout signal when they are equal. This timer includes a constantly incrementing counter to address a register that includes a multiple of timeout condition specifications, and as a determination of when the timeout conditions stored in the register occur.
Inventors
- 👤 Roger N. Bailey
- 👤 Robert L. Mansfield
- 👤 Alexander K. Spencer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:10
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757; G04; G04G; G04G15/00; G04G15/006; G06F1/00; G06F1/04; G06F1/14
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
93 words
A timer comprising: counter means for repetitively providing a current output each having an iteratively increasing sequence of bits relative to a preceding output; timeout data means for forming a timeout data word from a specified time period and a first counter means output; register means for storing said timeout data word at an address formed from said first counter means output; and comparison means for comparing each counter means output with a timeout data word at an address formed from said each counter means output and providing a timeout signal when equal.
Claim 2
Dependent Claim
93 words
A timer comprising: counter means for repetitively providing a current output each having an iteratively increasing sequence of bits relative to a preceding output; timeout data means for forming a timeout data word from a specified time period and a first counter means output; register means for storing said timeout data word at an address formed from said first counter means output; and comparison means for comparing each counter means output with a timeout data word at an address formed from said each counter means output and providing a timeout signal when equal.
Claim 3
Dependent Claim
31 words
A timer according to claim 1 wherein said first counter means output is the counter means output at the time the specified time period is received by said timeout data means.
Claim 4
Dependent Claim
31 words
A timer according to claim 2 wherein said specified time period includes information specifying which bits of the first counter means output are to be altered to specify said time period.
Claim 5
Dependent Claim
27 words
A timer according to claim 3 wherein said information also includes a specific one of a plurality of timeout signals to be provided by said comparison means.
Claim 6
Dependent Claim
34 words
A timer according to claim 4 wherein said information includes specified bits of the timeout data word to be ignored when said comparison means compares each counter means output with the timeout data word.
Claim 7
Dependent Claim
22 words
A timer according to claim 5 wherein said address is formed from a least significant plurality of bits of said counter output.
Claim 8
Dependent Claim
24 words
A timer according to claim 6 wherein said timeout data word is formed from a most significant plurality of bits of said counter output.
Claim 9
Dependent Claim
30 words
A timer according to claim 7 wherein said register means stores a status bit for each timeout data word indicating whether a timeout has occurred for that timeout data word.
Claim 10
Dependent Claim
153 words
A timer comprising: counter means for repetitively providing a current output each having an iteratively increasing sequence of bits relative to a preceding output; timeout data means for receiving information defining a timeout time and for providing a timeout data word formed from said information and a first portion of a first one of said counter means outputs; register means for receiving and storing said timeout data word from said timeout data means at an address specified by a second portion of said first one of said counter means outputs; and comparison means for comparing a first portion of each current counter means output with a first portion of said stored timeout data word in said register means stored at an address specified by a second portion of said current counter means output and providing a timeout signal when said timeout data word portion is equal to said current counter means first portion.
Claim 11
Dependent Claim
153 words
A timer comprising: counter means for repetitively providing a current output each having an iteratively increasing sequence of bits relative to a preceding output; timeout data means for receiving information defining a timeout time and for providing a timeout data word formed from said information and a first portion of a first one of said counter means outputs; register means for receiving and storing said timeout data word from said timeout data means at an address specified by a second portion of said first one of said counter means outputs; and comparison means for comparing a first portion of each current counter means output with a first portion of said stored timeout data word in said register means stored at an address specified by a second portion of said current counter means output and providing a timeout signal when said timeout data word portion is equal to said current counter means first portion.
Claim 12
Dependent Claim
31 words
A timer according to claim 9 wherein said first counter means output is the counter means output at a time a specified time period is received by said timeout data means.
Claim 13
Dependent Claim
31 words
A timer according to claim 10 wherein said information specifies which bits of the first portion of the first counter means output are to be altered to specify said time period.
Claim 14
Dependent Claim
27 words
A timer according to claim 11 wherein said information also includes a specific one of a plurality of timeout signals to be provided by said comparison means.
Claim 15
Dependent Claim
39 words
A timer according to claim 12 wherein said information includes specified bits of the timeout data word to be ignored when said comparison means compares the first portion of each current counter means output with the timeout data word.
Claim 16
Dependent Claim
21 words
A timer according to claim 13 wherein said second portion is a least significant plurality of bits of said counter output.
Claim 17
Dependent Claim
21 words
A timer according to claim 14 wherein said first portion is a most significant plurality of bits of said counter output.
Claim 18
Dependent Claim
30 words
A timer according to claim 15 wherein said register means stores a status bit for each timeout data word indicating whether a timeout has occurred for that timeout data word.
Claim 19
Dependent Claim
44 words
A timer according to claim 15 wherein said comparison means includes means, for resetting the status bit in said register means indicating that the timeout has occurred for that timeout data word when the timeout signal for that timeout data word has been provided.
Claim 20
Dependent Claim
26 words
A timer according to claim 17 wherein said register means includes means for storing a plurality of timeout data words each stored at a unique address.
Claim 21
Dependent Claim
56 words
A timer according to claim 18 wherein said timeout data means includes means for determining if a previously stored timeout data word, stored at an address of the second portion of the current counter means output, is still awaiting a timeout to occur, and, if not, storing a currently formed timeout data word at the address.
Claim 22
Dependent Claim
65 words
A timer according to claim 19 wherein said timeout data means includes means for waiting for a next address from a second portion of a next counter means output to store a currently formed timeout data word when the previously stored timeout data word stored at the address of the second portion of the current counter means output is awaiting for a timeout to occur.
Claim 23
Dependent Claim
145 words
A timer comprising: counter means for repetitively providing a current output, each having an iteratively increasing sequence of bits relative to a preceding output; a plurality of load signal means each for providing a load signal specifying a current output from the counter means and including means for specifying a timeout period; a plurality of register means each connected to an individual and unique one of said load signal means and for forming a timeout data word from said current counter means output and said specified time period from its connected load signal means and each including means for storing its respective timeout data word; and comparison means for comparing each successive counter means output with the timeout data word in each of said register means and providing a timeout signal when any one timeout data word is equal to the compared counter means output.
Claim 24
Dependent Claim
145 words
A timer comprising: counter means for repetitively providing a current output, each having an iteratively increasing sequence of bits relative to a preceding output; a plurality of load signal means each for providing a load signal specifying a current output from the counter means and including means for specifying a timeout period; a plurality of register means each connected to an individual and unique one of said load signal means and for forming a timeout data word from said current counter means output and said specified time period from its connected load signal means and each including means for storing its respective timeout data word; and comparison means for comparing each successive counter means output with the timeout data word in each of said register means and providing a timeout signal when any one timeout data word is equal to the compared counter means output.
Claim 25
Dependent Claim
87 words
A timer circuit according to claim 21 wherein at least one load signal means includes means for designating a specific timed event, said register means connected to said at least one load signal means includes means for storing data designating a specified time event and the comparison means includes means for providing a signal designating that a timed event has occurred when the timeout data word for the register means connected to said at least one load signal means is equal to the compared counter means output.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-29 | 1994-10-29 | 1995-04-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-29 | 1998-10-29 | 1999-04-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-29 | 2002-10-29 | 2003-04-30 | $7700.00 | Window Closed / Lapsed |