Time interval comparison system

Claim 2

A timer comprising: a. recording means to record a standard interval of time; b. measuring means to measure a subsequent interval of time; c. comparison means connected to said first and second means to compare said subsequent interval to said standard interval; d. first signal-generating means to generate a first signal following the beginning of said subsequent interval by an interval of time substantially equal to said standard interval; e. second signal-generating means to generate a second signal corresponding to the end of said subsequent interval; and f. discrepancy measuring means connected to said recording means and said first and second signal-generating means to measure the interval of time between said first and second signals as a percentage of said standard interval.

Claim 3

The timer of claim 1 in which said recording means comprises a digital storage register.

Claim 4

The timer of claim 2 in which said storage register comprises a series of electronic flip-flop circuits for storing information as to the duration of said standard interval in terms of electrical conditions of said flip-flops.

Claim 5

The timer of claim 1 in which both of said recording means and said measuring means comprise bistable circuits to store information in digitally related voltage form.

Claim 6

The timer of claim 1 comprising, in addition: a source of pulses and circuit means connecting said source of pulses to said recording means and to said measuring means; and control means to cause said source of pulses to supply pulses to said recording means during said standard interval of time and to apply said pulses to said measuring means during said subsequent interval of time.

Claim 7

The timer of claim 5 in which said connecting means from said source of pulses to said recording means comprises from said source of pulses to said recording means comprises a gate circuit to permit said pulses to reach said recording means only while said standard interval of time is being recorded.

Claim 8

The timer of claim 5 comprising, in addition: a second gate circuit; means to generate a control signal having a duration equal to said standard interval; means connecting said last-named means to said second gate circuit to control the operation of said second gate circuit to open said gate for a period of time equal to said standard interval; and means connecting said second gate circuit to said source of pulses to permit said pulses to be generated only during periods of time substantially equal to said standard interval.

Claim 9

The timer of claim 1 in which said recording means and said measuring means each comprises a series of electronic flip-flop circuits, each having a ''''O'''' condition and a ''''1'''' condition, and said comparison means comprises electronic logic circuits connected to corresponding flip-flops of said recording means and said measuring means to indicate by a voltage output condition whether both of the flip-flops connected to a particular comparison means are in the ''''0'''' condition or the ''''1'''' condition or whether one is in the ''''0'''' condition and the other is in the ''''1'''' condition.

Claim 10

In the timer of claim 8 a timing circuit comprising a plurality of capacitors arranged in sequency whereby the capacitance of the second capacitor in said sequence is twice as great as the capacitance of the first capacitor, the capacitance of the third capacitor in said sequence is twice as great as the capacitance of the capacitance of the second capacitor, and the capacitance of each subsequent capacitor in said sequence is twice as great as the capacitance of the capacitor immediately preceding it in said sequence, a plurality of transistors, each of said transistors connected in series with a respective one of said capacitors to form therewith a separate series charging circuit, and a connection between between the input circuit of each of said transistors and a respective one of said flip-flops in said storage register, whereby each of said transistors in conductive when the flip-flop to which it is connected is in its ''''1'''' condition and is nonconductive when the flip-flop to which it is connected is in its ''''0'''' condition, whereby each of said capacitors connected to conductive ones of said transistors are in parallel in said timing circuit, whereby the time constant of said timing circuit is proportional to the duration of said standard interval.

Claim 11

The timer of claim 9 comprising, in addition: a clamping transistor connected in parallel with each of said series circuits and comprising an input circuit; means to generate a pulse signal corresponding in duration to the discrepancy between said standard interval and a subsequent interval; and a connection from said last-named means to said input circuit of said clamping transistor to render said clamping transistor nonconductive for the duration of said discrepancy interval.

Claim 12

In the timer of claim 8, a timing circuit comprising: a third series of electronic flip-flop circuits, each having a ''''0'''' condition and a ''''1'''' condition, a series of comparison logic circuits, each connected to one flip-flop circuit of said third series and to a corresponding flip-flop circuit of said recording means to indicate by a voltage output condition whether both of the flip-flops connected to a particular comparison circuit are in the ''''0'''' condition or the ''''1'''' condition or whether one is in the ''''0'''' condition and the other in the ''''1'''' condition; a relatively high frequency pulse source having a repetition rate N times as great as the repetition rate of pulses of said first-named source; means to control the application of high frequency pulses from said high frequency source to said third series of flip-flop circuits; and means to indicate coincidence between all of the flip-flop circuits; and means to indicate coincidence between in said third series and all of the flip-flop circuits in said recording means.