Microcomputer retriggerable interval counter

Claim 2

A microcomputer having an interval counter for timing the duration between successive input signals so as to provide a maskable output interrupt signal which is indicative of said time duration and to which said microcomputer is responsive, said interval counter comprising: receiving means for storing a preset count number corresponding to a preset time duration; counting means for periodically decrementing a count number and producing said output interrupt signal when said count number is fully decremented and when the time interval between said input signals exceeds the count number; and control means responsive to the receipt of said input signals in order to cause said preset count number to be transferred from said receiving means to said counting means.

Claim 3

The interval counter of claim 1, wherein said control means responds to the production of an output interrupt signal by causing said preset number to be transferred from said receiving means to said counting means.

Claim 4

The interval counter of claim 1, wherein said control means prevents said counting means from producing an output interrupt signal when an input signal is received before said count number is fully decremented.

Claim 5

The interval counter of claim 1, wherein said receiving means comprises a digital latch for connection to a data bus so that a preset number in the form of digital binary bits corresponding to a desired preset time duration may be specified by loading said digital binary bits into said latch, and so that said digital binary bits may be transferred from said latch to said counting means when allowed by said control means.

Claim 6

The interval counter of claim 1, wherein said counting means comprises a digital down-counter for periodically decrementing the count number contained in said counter, and for producing an underflow timing indication when said count number has been decremented to zero.

Claim 7

The interval counter of claim 1, wherein said control means comprises: a down-load transfer gate for transferring numbers from said receiving means to said counting means; an OR gate having its output connected to actuate said down-load transfer gate, and having inputs responsive to said output interrupt signal of said counting means, and to said input signals so that the receipt of either said output interrupt signal or an input signal will cause the contents of said counting means to be set to said preset number contained in said receiving means.

Claim 8

The interval counter of claim 1 further comprising an edge detector means connected to said control means in order to condition said input signals by detecting the transitions in signal level of said input signals.

Claim 9

The interval counter of claim 1 further comprising a synchronizer means connected to said control means in order to selectively delay said input signals so that the receipt of said input signals by said control means is synchronized with the operation of said counting means.

Claim 10

A microcomputer having a central processor for executing instructions, memory for storing data and instructions, and a data bus for transferring information, wherein the improvement comprises an interval counter for measuring the time interval between successive input signals and providing a maskable output interrupt signal which is indicative of the time interval measured and to which said processor is responsive, said interval counter comprising: receiving means for receiving initialization information from said data bus; counting means for producing said output interrupt signal in response to said input signals and after a duration specified by said initialization information, and for providing said output interrupt signal to said processor; and control means connected to control said receiving means and said counting means so that when said output interrupt signal is received from said counting means, said control means initializes said counting means by automatically transferring said initialization information from said receiving means to said counting means.

Claim 11

A microcomputer having a central processor for executing instructions, memory for storing data and instructions, and a data bus for transferring information, wherein the improvement comprises an interval counter for measuring the time interval between successive input signals and providing a maskable output interrupt signal which is indicative of the time interval measured and to which said processor is responsive, said interval counter comprising: receiving means for receiving initialization information from said data bus; counting means for producing said output interrupt signal in response to said input signals and after a duration specified by said initialization information, and for providing said output interrupt signal to said processor; and control means connected to control said receiving means and said counting means so that when said output interrupt signal is received from said counting means, said control means initializes said counting means by automatically transferring said initialization information from said receiving means to said counting means.

Claim 12

The microcomputer of claim 9, wherein said initialization information defines a threshold interval duration so that time intervals longer than said threshold duration will cause an output interrupt signal to be produced by said interval counter, and so that time intervals shorter than said threshold duration will not cause an output interrupt signal to be produced by said interval counter.

Claim 13

The microcomputer of claim 9, wherein said receiving means comprises a digital buffer latch having inputs for the loading of a preset number as initialization information, and said interval counter further comprises a bus gate connected to said latch inputs and responsive to said processor for transferring a preset number from said data bus to said receiving means.

Claim 14

The microcomputer of claim 9, wherein said counting means comprises a digital down-counter for containing a digital count number and for periodically decrementing the count number to produce said an output interrupt signal when said count number has been decremented to zero.

Claim 15

The microcomputer of claim 12, wherein said counter has outputs and said interval counter further comprises a counter gate connected to said counter outputs and responsive to said processor for the transferring of said count number to said data bus.

Claim 16

The microcomputer of claim 9, wherein said control means comprises an OR gate having its output connected to control the transfer of specification information from said receiving means to said counting means, and having its inputs connected to respond to said an output interrupt signal of said counting means, and to respond to said input signals.

Claim 17

The microcomputer of claim 14, wherein said OR gate further has an input connected to respond to said processor so that processor instructions may be used to reset said counting means.

Claim 18

The microcomputer of claim 9 further comprising an edge detector means connected to said control means in order to condition said input pulses by detecting the transitions in signal level of said input pulses.

Claim 19

The microcomputer of claim 9 further comprising a synchronizer means connected to said control means in order to selectively delay said input signals so that the receipt of said input signals by said means for controlling is synchronized with the operation of said counting means.

Claim 20

The microcomputer of claim 9 further comprising a clock signal generating means connected to provide timing control to said processor and to said counting means.

Claim 21

An interval counter microcomputer for measuring the interval between successive input signals, said microcomputer comprising: counting means for producing a timing indication when the time interval between successive input signals exceeds a preset time interval, said counting means repeatedly decrementing a preset count number which corresponds to said preset time interval and which has become fully decremented during the time interval between said input signals; and processor means responsive to said timing indication for determining the interval between successive input signals.

Claim 22

An interval counter microcomputer for measuring the interval between successive input signals, said microcomputer comprising: counting means for producing a timing indication when the time interval between successive input signals exceeds a preset time interval, said counting means repeatedly decrementing a preset count number which corresponds to said preset time interval and which has become fully decremented during the time interval between said input signals; and processor means responsive to said timing indication for determining the interval between successive input signals.

Claim 23

The microcomputer of claim 19, wherein said counting means is retriggerable so that the production of timing indications is begun anew with the receipt of each of said input signals.