Patent US5012187A successfully refreshed from Google Patents.
US5012187A
Expired / Lapsed
US
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Method for parallel testing of semiconductor devices
Assignee: Motorola Solutions Inc
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Filing: 1989-11-03
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Granted: 1991-04-30
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Expires: 2009-11-03
Abstract
Abstract A method of testing unpackaged integrated circuits using a tester which is capable of testing a plurality of memories in parallel is provided. A membrane test head having a plurality of probe bumps thereon is provided wherein the probe bumps are coupled to the tester by microstrip transmission lines formed on the membrane test head. The semiconductor memory has a plurality of contact pads thereon which are coupled to the probes. In this manner, a plurality of semiconductor memories can be tested in wafer form. Alternatively, individual semiconductor memory chips can be mounted on a receiver plate and tested individually or in parallel by moving the receiver plate so that the contact pads couple to the probes.
Inventors
- 👤 Hugh W. Littlebury
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:44
CPC Classifications
G; G01; G01R; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R1/07307; G01R1/0735
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
103 words
A method of testing a plurality of semiconductor memory chips which are separated from a semiconductor wafer in which they were formed in parallel comprising the steps of: providing a tester which is capable of parallel testing memory devices; providing a flexible membrane having a plurality of probe bumps which are coupled to the tester; placing the individual memory chips on a receiver plate, wherein the receiver plate has a plurality of vacuum ports for holding the memory chips; testing access time of the plurality of memory chips in parallel; and storing information relating to location of memory chips which pass the test.
Claim 2
Independent Claim
103 words
A method of testing a plurality of semiconductor memory chips which are separated from a semiconductor wafer in which they were formed in parallel comprising the steps of: providing a tester which is capable of parallel testing memory devices; providing a flexible membrane having a plurality of probe bumps which are coupled to the tester; placing the individual memory chips on a receiver plate, wherein the receiver plate has a plurality of vacuum ports for holding the memory chips; testing access time of the plurality of memory chips in parallel; and storing information relating to location of memory chips which pass the test.
Claim 3
Dependent Claim
27 words
The method of claim 1 further comprising the steps of: removing the chips which pass the test from the receiver plate and mounting them on a leadframe.
Claim 4
Dependent Claim
29 words
The method of claim 1 wherein each of the probe bumps on the flexible membrane is coupled to the tester by a transmission line formed on the flexible membrane.
Claim 5
Independent Claim
188 words
A method for testing a plurality of integrated circuits which are separated from a semiconductor wafer in which they were formed, wherein each of the integrated circuits has a plurality of contact pads for electrical connection to the integrated circuit, the method comprising the steps of: providing a receiver plate having a vacuum port for each of the plurality of integrated circuits, wherein the vacuum port is sized to hold one of the integrated circuits; providing a well in the receiver plate surrounding each of the vacuum ports, wherein the well is sized to prevent substantial movement of the integrated circuit; providing a membrane probe having a plurality of probe bumps formed on one side of a flexible membrane, wherein the probe bumps are electrically coupled to a tester; placing each of the integrated circuits individually on the receiver plate covering one vacuum port; applying a vacuum to each of the vacuum ports; moving the receiver plate and/or the membrane probe so that the probe bumps couple to each of the plurality of contact pads of the plurality of integrated circuits; and testing the plurality of integrated circuits.
Claim 6
Independent Claim
188 words
A method for testing a plurality of integrated circuits which are separated from a semiconductor wafer in which they were formed, wherein each of the integrated circuits has a plurality of contact pads for electrical connection to the integrated circuit, the method comprising the steps of: providing a receiver plate having a vacuum port for each of the plurality of integrated circuits, wherein the vacuum port is sized to hold one of the integrated circuits; providing a well in the receiver plate surrounding each of the vacuum ports, wherein the well is sized to prevent substantial movement of the integrated circuit; providing a membrane probe having a plurality of probe bumps formed on one side of a flexible membrane, wherein the probe bumps are electrically coupled to a tester; placing each of the integrated circuits individually on the receiver plate covering one vacuum port; applying a vacuum to each of the vacuum ports; moving the receiver plate and/or the membrane probe so that the probe bumps couple to each of the plurality of contact pads of the plurality of integrated circuits; and testing the plurality of integrated circuits.
Claim 7
Dependent Claim
15 words
The method of claim 4 wherein the plurality of integrated circuits comprise semiconductor memory circuits.
Claim 8
Dependent Claim
19 words
The method of claim 4 wherein the tester is capable of testing a plurality of memory circuits in parallel.
Claim 9
Dependent Claim
27 words
The method of claim 4 wherein the membrane probe further comprises a ground plane formed on the same side of the flexible membrane as the probe bumps.
Claim 10
Dependent Claim
29 words
The method of claim 7 wherein the probe bumps are coupled to the tester by stripline conductors formed on a side of the flexible membrane opposite the probe bumps.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-29 | 1994-10-29 | 1995-04-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-29 | 1998-10-29 | 1999-04-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-29 | 2002-10-29 | 2003-04-30 | $7700.00 | Window Closed / Lapsed |