Programable logic array using one control clock signal

Claim 2

A programable logic array, comprising: an AND array and an OR array respectively composed of a plurality of second conductivity type MOS transistors; a plurality of first conductivity type MOS transistors of a first group each having one terminal connected to an electrical power source for supplying a predetermined voltage; and a plurality of first conductivity type MOS transistors of a second group each having one terminal connected to said electrical power source, wherein a true single clock signal is supplied to gate terminals of said first conductivity type MOS transistors of said second group; a complementary clock signal of said true single clock signal is supplied to gate terminals of said first conductivity type MOS transistors of said first group; and wherein a ratio of gate width W and gate length L, i.e., W/L, of each of said first conductivity type MOS transistors of said second group is smaller than that of said first conductivity type MOS transistors of said first group.

Claim 3

A programable logic array according to claim 1, wherein said first conductivity type MOS transistors are P channel type MOS transistors and said second conductivity type MOS transistors are N channel type MOS transistors.

Claim 4

A programable logic array, comprising: an AND array and an OR array respectively composed of a plurality of second conductivity type MOS transistors; a plurality of first conductivity type MOS transistors of a first group each having one terminal connected to an electrical power source for supplying a predetermined voltage; and a plurality of first conductivity type MOS transistors of a second group each having one terminal connected to said electrical power source, wherein a true single clock signal is supplied to gate terminals of said first conductivity type MOS transistors of said first group; a complementary clock signal of said true single clock signal is supplied to gate terminals of said first conductivity type MOS transistors of said second group; and wherein a ratio of gate width W and gate length L, i.e., W/L, of each of said first conductivity type MOS transistors of said first group is smaller than that of each of said first conductivity type MOS transistors of said second group.

Claim 5

A programable logic array, comprising: an AND array and an OR array respectively composed of a plurality of second conductivity type MOS transistors; a plurality of first conductivity type MOS transistors of a first group each having one terminal connected to an electrical power source for supplying a predetermined voltage; and a plurality of first conductivity type MOS transistors of a second group each having one terminal connected to said electrical power source, wherein a true single clock signal is supplied to gate terminals of said first conductivity type MOS transistors of said first group; a complementary clock signal of said true single clock signal is supplied to gate terminals of said first conductivity type MOS transistors of said second group; and wherein a ratio of gate width W and gate length L, i.e., W/L, of each of said first conductivity type MOS transistors of said first group is smaller than that of each of said first conductivity type MOS transistors of said second group.

Claim 6

A programable logic array according to claim 3, wherein said first conductivity type a MOS transistors are P channel type MOS transistors and said second conductivity type MOS transistors are N channel type MOS transistors.

Claim 7

A programable logic array, comprising: a plurality of first conductivity type MOS transistors of a second group each having a gate terminal and two other terminals, each said gate terminal of which receives a true single clock signal, and one of said other terminals being connected to an electrical power source; a OR array comprising a plurality of second conductivity type MOS transistors having a gate terminal and two other terminals, each said gate terminal of which is connected to one of a plurality of product term lines, and one of said other terminals of which is connected to a respective output line, another terminal of which is connected to ground; a plurality of first conductivity type MOS transistors of a first group each having a gate terminal thereof receiving a complementary clock signal of said true single clock signal; and an AND array comprising a plurality of second conductivity type MOS transistors each having a gate terminal and two other terminals, each said gate terminal receiving an input signal, one of said two other terminals of which is connected to one of said first conductivity type MOS transistors through one of said product term lines, another terminal of which is connected to ground; whereby discharge and charge holding of said second conductivity type MOS transistors in said AND array and said OR array are carried out in accordance with levels of said input signal and said single control clock signal, a stationary current is controlled so as to not flow in one array of said arrays during charge holding in the other array, and an output value of said OR array is outputted corresponding to said input signal, wherein a ratio of gate width W and gate length L, i.e., W/L, of each of said first conductivity type MOS transistors of said second group is smaller than that of each of said first conductivity type MOS transistors of said first group.

Claim 8

A programable logic array, comprising: a plurality of first conductivity type MOS transistors of a second group each having a gate terminal and two other terminals, each said gate terminal of which receives a true single clock signal, and one of said other terminals being connected to an electrical power source; a OR array comprising a plurality of second conductivity type MOS transistors having a gate terminal and two other terminals, each said gate terminal of which is connected to one of a plurality of product term lines, and one of said other terminals of which is connected to a respective output line, another terminal of which is connected to ground; a plurality of first conductivity type MOS transistors of a first group each having a gate terminal thereof receiving a complementary clock signal of said true single clock signal; and an AND array comprising a plurality of second conductivity type MOS transistors each having a gate terminal and two other terminals, each said gate terminal receiving an input signal, one of said two other terminals of which is connected to one of said first conductivity type MOS transistors through one of said product term lines, another terminal of which is connected to ground; whereby discharge and charge holding of said second conductivity type MOS transistors in said AND array and said OR array are carried out in accordance with levels of said input signal and said single control clock signal, a stationary current is controlled so as to not flow in one array of said arrays during charge holding in the other array, and an output value of said OR array is outputted corresponding to said input signal, wherein a ratio of gate width W and gate length L, i.e., W/L, of each of said first conductivity type MOS transistors of said second group is smaller than that of each of said first conductivity type MOS transistors of said first group.

Claim 9

A programable logic array according to claim 5, wherein said first conductivity type MOS transistors are P channel type MOS transistors and said second conductivity type MOS transistors are N channel type MOS transistors.

Claim 10

A programable logic array, comprising: a plurality of first conductivity type MOS transistors of a second group each having a gate terminal and two other terminals, each said gate terminal receiving a true single control clock signal, and one of said other terminals connected to an electrical power source; an OR array comprising a plurality of second conductivity type MOS transistors each having a gate terminal and two other terminals, each said gate terminal of said second conductivity type transistors connected to one of a plurality of product term lines, and one of said other terminals connected to a respective output line, with another terminal connected to ground; a plurality of first conductivity type MOS transistors of a first group having a gate terminal and two other terminals, each said gate terminal thereof receiving a complementary clock signal of said true single clock signal; and an AND array comprising a plurality of second conductivity type MOS transistors having a gate terminal and two other terminals, each said gate terminal of which receives an input signal, one of said two other terminals of which is connected to one of said first conductivity type MOS transistors through one of said product term lines, with another terminal of which connected to ground; whereby discharge and charge holding of said second conductivity type MOS transistors in said AND array and said OR array are carried out in accordance with levels of said input signal and said single control clock signal, a stationary current is controlled so as to not flow in one array of both said arrays during charge holding in the other array, and an output value of said OR array is outputted corresponding to said input signal, wherein a ratio of gate width W and gate length L, i.e., W/L, of each the said first conductivity type MOS transistors of said first group is smaller than that of each of said first conductivity type MOS transistors of said second group.

Claim 11

A programable logic array, comprising: a plurality of first conductivity type MOS transistors of a second group each having a gate terminal and two other terminals, each said gate terminal receiving a true single control clock signal, and one of said other terminals connected to an electrical power source; an OR array comprising a plurality of second conductivity type MOS transistors each having a gate terminal and two other terminals, each said gate terminal of said second conductivity type transistors connected to one of a plurality of product term lines, and one of said other terminals connected to a respective output line, with another terminal connected to ground; a plurality of first conductivity type MOS transistors of a first group having a gate terminal and two other terminals, each said gate terminal thereof receiving a complementary clock signal of said true single clock signal; and an AND array comprising a plurality of second conductivity type MOS transistors having a gate terminal and two other terminals, each said gate terminal of which receives an input signal, one of said two other terminals of which is connected to one of said first conductivity type MOS transistors through one of said product term lines, with another terminal of which connected to ground; whereby discharge and charge holding of said second conductivity type MOS transistors in said AND array and said OR array are carried out in accordance with levels of said input signal and said single control clock signal, a stationary current is controlled so as to not flow in one array of both said arrays during charge holding in the other array, and an output value of said OR array is outputted corresponding to said input signal, wherein a ratio of gate width W and gate length L, i.e., W/L, of each the said first conductivity type MOS transistors of said first group is smaller than that of each of said first conductivity type MOS transistors of said second group.

Claim 12

A programable logic array according to claim 7, wherein said first conductivity type MOS transistors are P channel type MOS transistors and said second conductivity type MOS transistors are N channel type MOS transistors.