Patent US5010032A successfully refreshed from Google Patents.
US5010032A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects
Assignee: Texas Instruments Inc
•
Filing: 1989-10-05
•
Granted: 1991-04-23
•
Expires: 2009-10-05
Abstract
Abstract A process for making CMOS device wherein the N-channel devices have n+ gates, and the P-channel devices have p+ gates. A TiN local interconnect system is used to connect the two types of gates, as well as providing connections to moat. A titanium nitride layer may be formed by depositing titanium metal everywhere, and then heating the integrated circuit structure in a nitrogen atmosphere. This process may also be used with other refractory metal nitride interconnect layers. In addition to titanium based thin film compositions, other metals can be substituted and used for direct-react silicidation and simultaneous formation of a conductive nitride to form local interconnects, including molybdenum, tungsten, vanadium, cobalt, and others.
Inventors
- 👤 Thomas E. Tang
- 👤 Che-Chia Wei
- 👤 Roger A. Haken
- 👤 Richard A. Chapman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:50
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B10/00; H10B10/12; H10B10/125; H10B41/42; H10B41/43; H10B41/48; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0172; H10D84/0174; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6316; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/066; H10W20/0698; Y; Y10; Y10S; Y10S148/00; Y10S148/147
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
254 words
A method for fabricating an integrated circuit at a silicon surface of a semiconductor body, comprising the steps of: forming a device isolation structure at said surface to define first and second moat regions at said surface adjacent to said device isolation structure, said first moat region of a first conductivity type and said second moat region of a second conductivity type; forming a first gate electrode comprising silicon doped to said second conductivity type overlying said first moat region, and a second gate electrode comprising silicon doped to said first conductivity type over said second moat region; forming source and drain regions at the surface of said first and second moat regions adjacent said first and second gate electrodes, said source and drain regions in said first moat region of said second conductivity type, and said source and drain regions in said second moat region of said first conductivity type; depositing titanium metal over said moat region and said device isolation structure; heating said body and said titanium metal in a nitrogen-bearing atmosphere, so that said titanium metal reacts with silicon of said gate electrodes to form a titanium silicide thereat, and so that said titanium metal also reacts with said nitrogen atmosphere to form a layer overlying said device isolation structure which comprises titanium nitride; and removing selected portions of said titanium nitride layer so that a remaining portion thereof provides an interconnection overlapping said device isolation structure, and in contact with said titanium silicide at said first and second gate electrodes.
Claim 2
Independent Claim
254 words
A method for fabricating an integrated circuit at a silicon surface of a semiconductor body, comprising the steps of: forming a device isolation structure at said surface to define first and second moat regions at said surface adjacent to said device isolation structure, said first moat region of a first conductivity type and said second moat region of a second conductivity type; forming a first gate electrode comprising silicon doped to said second conductivity type overlying said first moat region, and a second gate electrode comprising silicon doped to said first conductivity type over said second moat region; forming source and drain regions at the surface of said first and second moat regions adjacent said first and second gate electrodes, said source and drain regions in said first moat region of said second conductivity type, and said source and drain regions in said second moat region of said first conductivity type; depositing titanium metal over said moat region and said device isolation structure; heating said body and said titanium metal in a nitrogen-bearing atmosphere, so that said titanium metal reacts with silicon of said gate electrodes to form a titanium silicide thereat, and so that said titanium metal also reacts with said nitrogen atmosphere to form a layer overlying said device isolation structure which comprises titanium nitride; and removing selected portions of said titanium nitride layer so that a remaining portion thereof provides an interconnection overlapping said device isolation structure, and in contact with said titanium silicide at said first and second gate electrodes.
Claim 3
Dependent Claim
19 words
The method of claim 1, further comprising the subsequent step of annealing said titanium silicide to lower its resistivity.
Claim 4
Dependent Claim
44 words
The method of claim 2, wherein said heating step is performed at a temperature in the range of 500 to 750 degress C, and said subsequent silicide annealing step is performed at a higher temperature in the range of 700 to 875 degrees C.
Claim 5
Dependent Claim
19 words
The method of claim 1, wherein said titanium metal is applied to a thickness of less than 2000 angstroms.
Claim 6
Dependent Claim
23 words
The method of claim 1, wherein said heating step is performed at a temperature in the range of 500 to 750 degrees Centigrade.
Claim 7
Dependent Claim
77 words
The method of claim 1, wherein said step of removing selected portions of said titanium nitride layer comprises: forming an oxide hardmask over said titanium nitride layer at a location which extends over said device isolation structure, and said first and second gate electrodes; and etching said titanium nitride layer so that the portions thereof not underlying said oxide hardmask are removed, and so that a portion of said titanium nitride layer underlying said oxide hardmask remains.
Claim 8
Dependent Claim
79 words
The method of claim 1, wherein said step of removing selected portions of said titanium nitride layer comprises: forming an implant-hardened photoresist layer over said titanium nitride layer at a location which extends over said device isolation structure, and said first and second gate electrodes; etching said titanium nitride layer so that the portions thereof not underlying said implant-hardened photoresist layer are removed, and so that a portion of said titanium nitride layer underlying said implant-hardened photoresist layer remains.
Claim 9
Dependent Claim
74 words
The method of claim 1, wherein said step of removing selected portions of said titanium nitride layer comprises: performing a patterned implant to said titanium nitride layer in a location which extends over said device isolation structure and said first and second gate electrodes; and etching said titanium nitride layer after said step of performing a patterned implant, wherein said patterned implant imparts differential resistance of said titanium nitride layer to said etching step.
Claim 10
Dependent Claim
14 words
The method of claim 8, wherein said patterned implant comprises a patterned oxygen implant.
Claim 11
Dependent Claim
26 words
The method of claim 1, wherein said step of removing selected portions of said titanium nitride layer comprises etching said layer with a substantially isotropic etch.
Claim 12
Independent Claim
251 words
A method for fabricating an integrated circuit at a silicon surface of a semiconductor body, comprising the steps of: forming a device isolation structure at said surface to define first and second moat regions at said surface adjacent to said device isolation structure, said first moat region of a first conductivity type and said second moat region of a second conductivity type; forming a first gate electrode comprising silicon doped to said second conductivity type overlying said first moat region, and a second gate electrode comprising silicon doped to said first conductivity type over said second moat region; forming source and drain regions at the surface of said first and second moat regions adjacent said first and second gate electrodes, said source and drain regions in said first moat region of said second conductivity type, and said source and drain regions in said second moat region of said first conductivity type; depositing a refractory metal over said moat region and said device isolation structure; heating said body and said refractory metal in a nitrogen-bearing atmosphere, so that first regions of said refractory metal react with silicon of said gate electrodes to form refractory metal silicide thereat, and so that a second region of said refractory metal reacts to form a diffusion resistant refractory metal nitride; and removing selected portions of the refractory metal nitride so that a remaining portion thereof provides an interconnection overlapping said device isolation structure, and in contact with said silicide at said first and second gate electrodes.
Claim 13
Independent Claim
251 words
A method for fabricating an integrated circuit at a silicon surface of a semiconductor body, comprising the steps of: forming a device isolation structure at said surface to define first and second moat regions at said surface adjacent to said device isolation structure, said first moat region of a first conductivity type and said second moat region of a second conductivity type; forming a first gate electrode comprising silicon doped to said second conductivity type overlying said first moat region, and a second gate electrode comprising silicon doped to said first conductivity type over said second moat region; forming source and drain regions at the surface of said first and second moat regions adjacent said first and second gate electrodes, said source and drain regions in said first moat region of said second conductivity type, and said source and drain regions in said second moat region of said first conductivity type; depositing a refractory metal over said moat region and said device isolation structure; heating said body and said refractory metal in a nitrogen-bearing atmosphere, so that first regions of said refractory metal react with silicon of said gate electrodes to form refractory metal silicide thereat, and so that a second region of said refractory metal reacts to form a diffusion resistant refractory metal nitride; and removing selected portions of the refractory metal nitride so that a remaining portion thereof provides an interconnection overlapping said device isolation structure, and in contact with said silicide at said first and second gate electrodes.
Claim 14
Dependent Claim
20 words
The method of claim 11, further comprising the subsequent step of annealing said refractory metal silicide to lower its resistivity.
Claim 15
Dependent Claim
19 words
The method of claim 11, wherein said refractory metal is applied to a thickness of less than 2000 angstroms.
Claim 16
Dependent Claim
23 words
The method of claim 11, wherein said heating steps is performed at a temperature in the range of 500 to 750 degrees centigrade.
Claim 17
Dependent Claim
44 words
The method of claim 12, wherein said heating step is performed at a temperature in the range of 500 to 750 degrees C. and said subsequent silicide annealing step is performed at a higher temperature in the range of 700 to 875 degrees C.
Claim 18
Dependent Claim
78 words
The method of claim 11, wherein said step of removing elected portions of said refractory metal nitride comprises: forming an oxide hardmask over said refractory metal nitride at a location which extends over said device isolation structure and over said first and second gatge electrodes; and etching said refractory metal nitride so that the portions thereof not underlying said oxide hardmask are removed, and so that a portion of said refractory metal nitride underlying said oxide hardmask remains.
Claim 19
Dependent Claim
81 words
The method of claim 11, wherein said step of removing selected portions of said refractory metal nitride comprises: forming a hardened photoresist layer over said refractory metal nitride at a location which extends over said device isolation structure and over said first and second gate electrodes; and etching said refractory metal nitride so that the portions thereof not underlying said implant-hardened photoresist layer are removed, and so that a portion of said refractory metal nitride underlying said implanthardened photoresist layer remains.
Claim 20
Dependent Claim
74 words
The method of claim 11, wherein said step of removing selected portions of said refractory metal nitride comprises: performing a patterned implant to said refractory metal nitride in a location which extends over said device isolation structure and said first and second gate electrodes; and etching said refractory metal nitride after said step of performing a patterned implant, wherein said patterned implant imparts differential resistance of said refractory metal nitride to said etching step.
Claim 21
Dependent Claim
14 words
The method of claim 18, wherein said patterned implant comprises a patterned oxygen implant.
Claim 22
Dependent Claim
26 words
The methodd of claim 11, wherein said step of removing selected portionsn of said refractory metal nitride comprises etching said layer with a substantially isotropic etch.
Claim 23
Dependent Claim
24 words
The method of claim 11, wherein said refractory metal is selected from the group consisting of at least one of titanium, molybdenum and tungsten.
Claim 24
Independent Claim
260 words
A method for fabricating an integrated circuit at a silicon surface of a semiconductor body, comprising the steps of: forming a device isolation structure at said surface to define first and second moat regions at said surface adjacent to said device isolation structure, said first moat region of a first conductivity type and said second moat region of a second conductivity type; forming a first gate electrode comprising silicon doped to said second conductivity type overlying said first moat region, and a second gate electrode comprising silicon doped to said first conductivity type over said second moat region; forming source and drain regions at the surface of said first and second moat regions adjacent said first and second gate electrodes, said source and drain regions in said first moat region of said second conductivity type, and said source and drain regions in said second moat region of said first conductivity type; depositing a metal selected from the group consisting of at least one of titanium, molybdenum, tungsten, vandium and cobalt over said moat region and said device isolation structure; heating said body and said metal in a nitrogen-bearing atmosphere, so that some regions of said metal reacts with silicon of said gate electrodes to form a metal silicide thereat, and other regions react with nitrogen to form a metal nitride layer in other regions; and removing selected portions of the metal nitride layer so that a remaining portion thereof provides an interconnection overlapping said device isolation structure, and in contact with said silicide at said first and second gate electrodes.
Claim 25
Independent Claim
260 words
A method for fabricating an integrated circuit at a silicon surface of a semiconductor body, comprising the steps of: forming a device isolation structure at said surface to define first and second moat regions at said surface adjacent to said device isolation structure, said first moat region of a first conductivity type and said second moat region of a second conductivity type; forming a first gate electrode comprising silicon doped to said second conductivity type overlying said first moat region, and a second gate electrode comprising silicon doped to said first conductivity type over said second moat region; forming source and drain regions at the surface of said first and second moat regions adjacent said first and second gate electrodes, said source and drain regions in said first moat region of said second conductivity type, and said source and drain regions in said second moat region of said first conductivity type; depositing a metal selected from the group consisting of at least one of titanium, molybdenum, tungsten, vandium and cobalt over said moat region and said device isolation structure; heating said body and said metal in a nitrogen-bearing atmosphere, so that some regions of said metal reacts with silicon of said gate electrodes to form a metal silicide thereat, and other regions react with nitrogen to form a metal nitride layer in other regions; and removing selected portions of the metal nitride layer so that a remaining portion thereof provides an interconnection overlapping said device isolation structure, and in contact with said silicide at said first and second gate electrodes.
References Cited (Backward Citations)
US4253888A
Cited
US4314874A
Cited
US4333226A
Cited
US4442591A
Cited
US4682403A
Cited
US4657628A
Cited
US4676866A
Cited
US4890141A
Cited
US4931411A
Cited
US4746219A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-22 | 1994-10-22 | 1995-04-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-22 | 1998-10-22 | 1999-04-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-22 | 2002-10-22 | 2003-04-23 | $7700.00 | Window Closed / Lapsed |