Universal shift register employing a matrix of transmission gates

Claim 2

A universal shift register having a plurality M of selectable operating modes where M is an integer, the shift register comprising: a plurality N of bistable storage devices where N is an integer, one for each stage of the shift register; means for indicating any one of the M selectable operating modes for the shift register; and an N column-by-M row matrix of information transmission gates coupled to the indicating means and to the N bistable storage devices, each of the M rows of the matrix arranged to perform one of the selectable register operating modes upon each of the N register stages, whereby register stage data pass through only a single information transmission gate of the matrix while being manipulated between a shift register input and a predetermined shift register stage.

Claim 3

A universal shift register having a plurality M of selectable operating modes where M is an integer, the shift register comprising: a plurality N of bistable storage devices where N is an integer, one for each stage of the shift register; means for indicating any one of the M selectable operating modes for the shift register; an N column by M row matrix of information transmission gates coupled to the indicating means and to the N bistable storage devices, and arranged such that each of the M rows of the matrix performs one of the selectable register operating modes upon each of the N register stages, such that register stage data pass through only a single information transmission gate of the matrix while being manipulated between a shift register input and a predetermined shift register stage; and means for enabling cascaded connection of the shift register to at least one additional shift register of similar design.

Claim 4

A universal shift register having a plurality M of selectable operating modes where M is an integer, the shift register comprising: a plurality N of bistable storage devices where N is an integer, one for each stage of the shift register; means for indicating any one of the M selectable operating modes for the shift register; an N column by M row matrix of information transmission gates coupled to the indicating means and to the N bistable storage devices, and arranged such that each of the M rows of the matrix performs one of the selectable register operating modes upon each of the N register stages, such that register stage data pass through only a single information transmission gate of the matrix while being manipulated between a shift register input and a predetermined shift register stage; and means for enabling cascaded connection of the shift register to at least one additional shift register of similar design.

Claim 5

A universal shift register having a plurality M of selectable operating modes, the shift register comprising: a plurality N of flip-flops, one for each stage of the shift register, M and N being integers; decoding logic means coupled for receipt of a variable mode selection signal indicative of any one of the M operating modes and having M output, each assuming a predetermined logic state whenever a corresponding operating mode is indicated by the mode selection signal; and a matrix of data transmission gates comprised of M rows and N columns, each transmission gate having a data input, a control input and a data output and operative to pass data presented to the data input to the data output whenever a predetermined signal is presented to the control input, the control inputs of each row of the matrix being commonly coupled to one of the M outputs of the decoding logic means, the data outputs of each column of the matrix being commonly coupled to one of the N flip-flop register stages, and the data inputs being arranged such that a different shift register data manipulation function may be effected by the activation of each different matrix row of transmission gates via the commonly coupled control inputs for each row, whereby register stage data pass through only a single information transmission gate of the matrix while being manipulated between a shift register input and a predetermined shift register stage.

Claim 6

A universal shift register having a plurality M of selectable operating modes, the shift register comprising: a plurality N of flip-flops, one for each stage of the shift register, M and N being integers; decoding logic means coupled for receipt of a variable mode selection signal indicative of any one of the M operating modes and having M output, each assuming a predetermined logic state whenever a corresponding operating mode is indicated by the mode selection signal; and a matrix of data transmission gates comprised of M rows and N columns, each transmission gate having a data input, a control input and a data output and operative to pass data presented to the data input to the data output whenever a predetermined signal is presented to the control input, the control inputs of each row of the matrix being commonly coupled to one of the M outputs of the decoding logic means, the data outputs of each column of the matrix being commonly coupled to one of the N flip-flop register stages, and the data inputs being arranged such that a different shift register data manipulation function may be effected by the activation of each different matrix row of transmission gates via the commonly coupled control inputs for each row, whereby register stage data pass through only a single information transmission gate of the matrix while being manipulated between a shift register input and a predetermined shift register stage.

Claim 7

The shift register of claim 3 wherein one of the M operating modes comprises a parallel data register input function and wherein one of the M matrix rows corresponding to the parallel input function has each of the data inputs in the one matrix row respectively coupled to one of N external data input lines.

Claim 8

The shift register of claim 3 wherein one of the M operating modes comprises a shift-right function and wherein one of the M matrix rows corresponding to the shift-right function has the data input of its transmission gate associated with the first register stage coupled for receipt of external serial data and the data inputs of the remaining gates in the one matrix row coupled to an output of a preceding register flip-flop stage.

Claim 9

The shift register of claim 3 wherein one of the M operating modes comprises a shift-left function and wherein one of the M matrix rows corresponding to the shift-left function has the data input of its transmission gate associated with the last register stage coupled for receipt of external serial data and the data inputs of the remaining gates in the one matrix row coupled to an output of a succeeding register flip-flop stage.

Claim 10

The shift register of claim 3 wherein one of the M operating modes comprises a hold function and wherein one of the M matrix rows corresponding to the hold function has the data input of each transmission gate in the one matrix row coupled to an output of the corresponding register flip-flop stage associated with the column in which each transmission gate is positioned within the matrix.

Claim 11

The shift register of claim 3 further comprising means enabling cascading of the N-stage shift register with at least one additional shift register of similar design.

Claim 12

In a universal shift register having a plurality M of selectable operating modes where M is an integer, a plurality N of bistable storage devices where N is an integer, one for each register stage, means for indicating any one of the M operating modes, and means coupled between the bistable storage devices and the means for indicating for effecting any one of the operating modes, the improvement comprising arranging an N column by M row array of high speed data transmission gates to form the means for effecting, each of the M rows of the matrix arranged to perform one of the M selectable operating modes upon each of the N register stages, whereby register stage data pass through only a single information transmission gate of the matrix while being manipulated between a shift register input and a predetermined shift register stage.

Claim 13

In a universal shift register having a plurality M of selectable operating modes where M is an integer, a plurality N of bistable storage devices where N is an integer, one for each register stage, means for indicating any one of the M operating modes, and means coupled between the bistable storage devices and the means for indicating for effecting any one of the operating modes, the improvement comprising arranging an N column by M row array of high speed data transmission gates to form the means for effecting, each of the M rows of the matrix arranged to perform one of the M selectable operating modes upon each of the N register stages, whereby register stage data pass through only a single information transmission gate of the matrix while being manipulated between a shift register input and a predetermined shift register stage.