US5008668A
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Method and apparatus for encoding and decoding data in residue number system
Assignee: Sony Corp
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Filing: 1988-10-12
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Granted: 1991-04-16
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Expires: 2008-10-12
Abstract
Abstract In a method and apparatus for encoding and decoding data in the residue number system, input binary data are supplied to an encoder to be divided by moduli m 0 , m 1 , m 2 , . . . m (i.e., positive integers having a mutually prime relation). Residue data corresponding to respective moduli are output from the encoder to a digital filter circuit including a plurality of digital filters, each filter corresponding to a respective modulus. Processing for some specified application is performed by the digital filters based, for example, on the Mixed Radix Conversion Method method to generate output data still in the residue format. The residue data output from the digital filters then are input to a decoder to be converted back into binary data. Encoding is performed by splitting n-bit straight binary data into, for example, upper bit data and lower bit data, received by respective ROM tables. Each ROM table outputs a value to another common ROM table which outputs the converted residue data. The ROM tables convert the binary data by weighing each input bit by a value corresponding to the particular bit. The capacity needed for the ROM tables is reduced, enabling the encoder circuit configuration to be simple and fast. Decoding is performed by scaling down RNS data to obtain a plurality of residue data corresponding to respective moduli, adding one to a fixed bit of the residue data for discriminating positive and negative numbers, and performing addition on such residue data with fixed moduli to obtain binary data.
Inventors
- 👤 Jun Takayama
- 👤 Takeshi Ninomiya
- 👤 Tadao Fujita
- 👤 Yoshiaki Inaba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 20:06
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/14; H03M7/18
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
219 words
An encoder circuit for converting input data composed of binary codes into RNS data, comprising: dividing means using fixed bits of a predetermined length for dividing said input data having the value S into upper bit data S u and lower bit data having the value S L in the relation S=S.sub.u ×2.sup.q +S.sub.L in which 2 q is a weighted value; a first ROM table circuit for weighing each of said upper and lower bit data and converting said upper and lower bit data into residue data for respective fixed RNS moduli, said residue data having a value R i represented by the equation R i =(R ui +R Li ) MOD m i , wherein R ui is an upper bit residue data value R Li is a lower bit residue data value of a modulus m i ; a second ROM table circuit for converting an addition value of said residue data for each of said moduli into residue data of respective moduli and said addition value has a residue data value D i composed of the added values of lower bit residue data D L and upper bit residue data D u ; and means for outputting said residue data obtained from said second ROM table circuit as said residue data composing said RNS data.
Claim 2
Dependent Claim
219 words
An encoder circuit for converting input data composed of binary codes into RNS data, comprising: dividing means using fixed bits of a predetermined length for dividing said input data having the value S into upper bit data S u and lower bit data having the value S L in the relation S=S.sub.u ×2.sup.q +S.sub.L in which 2 q is a weighted value; a first ROM table circuit for weighing each of said upper and lower bit data and converting said upper and lower bit data into residue data for respective fixed RNS moduli, said residue data having a value R i represented by the equation R i =(R ui +R Li ) MOD m i , wherein R ui is an upper bit residue data value R Li is a lower bit residue data value of a modulus m i ; a second ROM table circuit for converting an addition value of said residue data for each of said moduli into residue data of respective moduli and said addition value has a residue data value D i composed of the added values of lower bit residue data D L and upper bit residue data D u ; and means for outputting said residue data obtained from said second ROM table circuit as said residue data composing said RNS data.
Claim 3
Dependent Claim
173 words
A decoding method for demodulating RNS data composed of residue data of a plurality of moduli into binary data by a Mixed Radix Conversion Method (MRC) using a multiplicative inverse element of a value of one modulus for that of another modulus to reduce the number of residue data, comprising the steps of: selecting one of said moduli to be a value represented by the power of 2 and said moduli has residue data value R i or residue data value R j of moduli m i or m j , respectively, applying to residue data scale-down processing performed in parallel pertaining to said one of said moduli represented by said power of 2 and said residue scale-down processing having a value R ji represented by the expression R ji ={(R i -R j )X ij }MOD m i , wherein X ij is a multiplicative inverse element of the modulus m j , and applying to said residue data scale-down processing pertaining to each of the remaining of said plurality of moduli.
Claim 4
Dependent Claim
173 words
A decoding method for demodulating RNS data composed of residue data of a plurality of moduli into binary data by a Mixed Radix Conversion Method (MRC) using a multiplicative inverse element of a value of one modulus for that of another modulus to reduce the number of residue data, comprising the steps of: selecting one of said moduli to be a value represented by the power of 2 and said moduli has residue data value R i or residue data value R j of moduli m i or m j , respectively, applying to residue data scale-down processing performed in parallel pertaining to said one of said moduli represented by said power of 2 and said residue scale-down processing having a value R ji represented by the expression R ji ={(R i -R j )X ij }MOD m i , wherein X ij is a multiplicative inverse element of the modulus m j , and applying to said residue data scale-down processing pertaining to each of the remaining of said plurality of moduli.
Claim 5
Dependent Claim
125 words
A decoder method for demodulating RNS data into binary data, comprising the steps of: scale-down processing the RNS data of a plurality of fixed moduli for obtaining a plurality of residue data corresponding to each of said moduli of the RNS data, said scale-down processing using multiplicative inverse values of the RNS set to the values of said moduli, addition processing said residue data with said fixed moduli, respectively, to obtain addition data, thereby demodulating the RNS data into binary data, said addition processing adding data D i which are bit-shifted by l bits, and adding the value 1 to a fixed bit of said RNS data to achieve fixed data intermediate said scale-down processing and said addition processing for discriminating positive and negative numbers.
Claim 6
Dependent Claim
125 words
A decoder method for demodulating RNS data into binary data, comprising the steps of: scale-down processing the RNS data of a plurality of fixed moduli for obtaining a plurality of residue data corresponding to each of said moduli of the RNS data, said scale-down processing using multiplicative inverse values of the RNS set to the values of said moduli, addition processing said residue data with said fixed moduli, respectively, to obtain addition data, thereby demodulating the RNS data into binary data, said addition processing adding data D i which are bit-shifted by l bits, and adding the value 1 to a fixed bit of said RNS data to achieve fixed data intermediate said scale-down processing and said addition processing for discriminating positive and negative numbers.
Claim 7
Dependent Claim
92 words
A decoder circuit for converting RNS data into unipolar binary data comprising: a data converting circuit for converting said RNS data into unipolar binary data; a discriminating circuit for adding a first fixed value to said binary data output from said data converting circuit and outputting the most significant bit of the result of said adding for discriminating between positive and negative numbers by the most significant bit, and an adder for adding a second fixed value to said unipolar binary data and outputting the result thereof as said bipolar binary data.
Claim 8
Dependent Claim
92 words
A decoder circuit for converting RNS data into unipolar binary data comprising: a data converting circuit for converting said RNS data into unipolar binary data; a discriminating circuit for adding a first fixed value to said binary data output from said data converting circuit and outputting the most significant bit of the result of said adding for discriminating between positive and negative numbers by the most significant bit, and an adder for adding a second fixed value to said unipolar binary data and outputting the result thereof as said bipolar binary data.
Claim 9
Dependent Claim
76 words
A decoder circuit comprising: a first data converting circuit for converting RNS data into binary data; an adder for adding the value 1 to a fixed bit of said binary data for discriminating between positive and negative numbers by the most significant bit, and a second data converting circuit for adding a fixed value to said binary data including said fixed bit added with the value 1, thereby converting said binary data into bipolar binary data.
Claim 10
Dependent Claim
76 words
A decoder circuit comprising: a first data converting circuit for converting RNS data into binary data; an adder for adding the value 1 to a fixed bit of said binary data for discriminating between positive and negative numbers by the most significant bit, and a second data converting circuit for adding a fixed value to said binary data including said fixed bit added with the value 1, thereby converting said binary data into bipolar binary data.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1994-04-15 | 1994-10-15 | 1995-04-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-15 | 1998-10-15 | 1999-04-16 | $3760.00 | Window Closed / Lapsed |
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